dhm2013724 / Xilinx_FPGA_HLS-Mapping-Neural-Network-to-Hardware
At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA
☆31Updated 6 years ago
Alternatives and similar repositories for Xilinx_FPGA_HLS-Mapping-Neural-Network-to-Hardware:
Users that are interested in Xilinx_FPGA_HLS-Mapping-Neural-Network-to-Hardware are comparing it to the libraries listed below
- ☆44Updated 6 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆109Updated 7 years ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.☆92Updated last year
- FPGA accelerator and port of the emotion recognition CNN running in C on Xilinx ZYNQ☆21Updated 5 years ago
- 中文:☆97Updated 5 years ago
- FPGA/AES/LeNet/VGG16☆99Updated 6 years ago
- ☆33Updated 5 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- A DNN Accelerator implemented with RTL.☆63Updated 2 months ago
- The CNN based on the Xilinx Vivado HLS☆37Updated 3 years ago
- 2019 SEU-Xilinx Summer School☆48Updated 5 years ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆111Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆86Updated 4 years ago
- ☆39Updated 6 years ago
- A VGG accelerator by System Verilog on DE1-SoC FPGA. Row Stationary (RS) dataflow is adopted, and computations are based on fixed point 1…☆30Updated 5 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆30Updated 5 years ago
- This TRD is implement DPU v1.4.0 on PYNQ-Z2 board☆44Updated 4 years ago
- A FPGA Based CNN accelerator, following Google's TPU V1.☆143Updated 5 years ago
- An LeNet RTL implement onto FPGA☆44Updated 6 years ago
- The second place winner for DAC-SDC 2020☆97Updated 2 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆37Updated 5 years ago
- FPGA accelerated TinyYOLO v2 object detection neural network☆71Updated 6 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- Deploy CNN accelerator in embedded OS using SDSOC and Xilinx Ultrascale+ ZCU102 platform.☆25Updated 6 years ago
- CNN-Accelerator based on FPGA developed by verilog HDL.☆46Updated 4 years ago
- Lenet for MNIST handwritten digit recognition using Vivado hls tool☆36Updated 4 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆50Updated 6 years ago