yycho0108 / CompArchNeuralNet
Final project for Computer Architecture FA16
☆14Updated 8 years ago
Alternatives and similar repositories for CompArchNeuralNet:
Users that are interested in CompArchNeuralNet are comparing it to the libraries listed below
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆65Updated last year
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆77Updated 5 years ago
- ☆26Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆20Updated 3 years ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆23Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆135Updated 6 months ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆121Updated 6 years ago
- ☆15Updated 3 weeks ago
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- IEEE Executive project for the year 2021-2022☆7Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- Vitis HLS Library for FINN☆188Updated last month
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆39Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆72Updated 6 years ago
- PYNQ Composabe Overlays☆69Updated 7 months ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆86Updated 2 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆9Updated 5 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆56Updated 5 months ago
- Architectural design of data router in verilog☆28Updated 5 years ago
- A collection of commonly asked RTL design interview questions☆22Updated 7 years ago
- UVM and System Verilog Manuals☆38Updated 5 years ago
- round robin arbiter☆70Updated 10 years ago
- This is a verilog implementation of 4x4 systolic array multiplier☆42Updated 4 years ago
- AXI Interconnect☆47Updated 3 years ago
- An AXI4 crossbar implementation in SystemVerilog☆130Updated last month
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆81Updated last year
- IC implementation of TPU☆92Updated 5 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆174Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆47Updated last year
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆100Updated 5 years ago