Alternatives and similar repositories for urv-core

Users that are interested in urv-core are comparing it to the libraries listed below

• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated 11 months ago
• RISCV-on-Microsemi-FPGA / SoftConsole
  Eclipse based IDE for RISC-V bare metal software development.
  ☆20Updated 6 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• CospanDesign / nysa-sata
  ☆89Updated 8 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆73Updated 8 years ago
• open-design / riscv-soc-cores
  ☆41Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆35Updated 4 years ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆24Updated 11 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated 3 weeks ago
• OpenDGPS / zynq-axi-dma-sg
  Simple C snippet to transfer DMA memory with scatter/gather on a Zynq 7020
  ☆56Updated 8 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆70Updated 7 years ago
• MIPSfpga / mipsfpga-plus
  MIPSfpga+ allows loading programs via UART and has a switchable clock
  ☆111Updated 6 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆48Updated 5 years ago
• tmbinc / xvcd
  Xilinx Virtual Cable Daemon
  ☆124Updated 10 months ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆63Updated 7 years ago
• derekmulcahy / xvcpi
  Xilinx Virtual Cable Server for Raspberry Pi
  ☆124Updated 3 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆46Updated 10 years ago
• enjoy-digital / daisho
  Test of the USB3 IP Core from Daisho on a Xilinx device
  ☆100Updated 6 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 7 years ago
• hamsternz / FPGA_GigabitTx
  Sending UDP packets out over a Gigabit PHY with an FPGA.
  ☆44Updated 9 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• micro-FPGA / riscv-contest-2018
  RISCV SoftCPU Contest 2018
  ☆14Updated 7 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆36Updated 11 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆68Updated 3 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆99Updated last year
• zhelnio / ahb_lite_sdram
  SDRAM controller for MIPSfpga+ system
  ☆24Updated 5 years ago