maikmerten / riscv-tomthumb
A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning
☆32Updated 6 years ago
Alternatives and similar repositories for riscv-tomthumb:
Users that are interested in riscv-tomthumb are comparing it to the libraries listed below
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- SoftCPU/SoC engine-V☆54Updated 2 weeks ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- CMod-S6 SoC☆40Updated 7 years ago
- Open Processor Architecture☆26Updated 8 years ago
- Extensible FPGA control platform☆59Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 3 weeks ago
- Wishbone interconnect utilities☆39Updated last month
- A wishbone controlled scope for FPGA's☆78Updated last year
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 7 years ago
- Verilog FT245 to AXI stream interface☆28Updated 6 years ago
- Spen's Official OpenOCD Mirror☆48Updated 3 weeks ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆35Updated 6 years ago
- Wishbone controlled I2C controllers☆47Updated 4 months ago
- TCP/IP controlled VPI JTAG Interface.☆65Updated 2 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- ☆63Updated 6 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- Universal Advanced JTAG Debug Interface☆17Updated 10 months ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Yet Another RISC-V Implementation☆91Updated 6 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 8 months ago
- FPGA optimized RISC-V (RV32IM) implemenation☆34Updated 4 years ago
- LatticeMico32 soft processor☆105Updated 10 years ago
- Repository and Wiki for Chip Hack events.☆50Updated 3 years ago
- Advanced Debug Interface☆14Updated 2 months ago
- Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores☆50Updated last year
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- Yosys Plugins☆21Updated 5 years ago