maikmerten / riscv-tomthumbLinks
A small RISC-V RV32I core written in VHDL, intended as testbed for my personal VHDL learning
☆32Updated 7 years ago
Alternatives and similar repositories for riscv-tomthumb
Users that are interested in riscv-tomthumb are comparing it to the libraries listed below
Sorting:
- Yosys Plugins☆21Updated 5 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆34Updated 8 years ago
- OpenFPGA☆34Updated 7 years ago
- Generic Logic Interfacing Project☆46Updated 4 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A wishbone controlled scope for FPGA's☆82Updated last year
- LatticeMico32 soft processor☆106Updated 10 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- a playground for xilinx zynq fpga experiments☆49Updated 6 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last month
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated last year
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆64Updated 7 years ago
- ☆63Updated 6 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- Wishbone <-> AXI converters☆14Updated 10 years ago
- Z-scale Microarchitectural Implementation of RV32 ISA☆55Updated 8 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆29Updated 6 years ago
- Eclipse based IDE for RISC-V bare metal software development.☆18Updated 5 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆32Updated 4 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- A padring generator for ASICs☆25Updated 2 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆96Updated 3 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- Universal Advanced JTAG Debug Interface☆17Updated last year
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago
- Open Processor Architecture☆26Updated 9 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆54Updated 2 years ago