rgwan / bapi-rv32iLinks
A extremely size-optimized RV32I soft processor for FPGA.
☆27Updated 6 years ago
Alternatives and similar repositories for bapi-rv32i
Users that are interested in bapi-rv32i are comparing it to the libraries listed below
Sorting:
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Python module containing verilog files for rocket cpu (for use with LiteX).☆14Updated last week
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- PicoRV☆44Updated 5 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- Repo that shows how to use the VexRiscv with OpenOCD and semihosting.☆25Updated 3 years ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆31Updated 4 years ago
- A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga☆26Updated 5 years ago
- ☆33Updated 2 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Updated 3 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 4 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆89Updated 4 years ago
- A RISC-V processor☆15Updated 6 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆29Updated 5 months ago
- ☆17Updated 2 years ago
- Chisel Cheatsheet☆33Updated 2 years ago
- Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.☆39Updated last year
- Naive Educational RISC V processor☆83Updated 7 months ago
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Trivial RISC-V Linux binary bootloader☆51Updated 4 years ago
- CMod-S6 SoC☆42Updated 7 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- Library of FPGA architectures☆21Updated 2 months ago
- GDB server to debug CPU simulation waveform traces☆44Updated 3 years ago