rgwan / bapi-rv32iLinks
A extremely size-optimized RV32I soft processor for FPGA.
☆28Updated 7 years ago
Alternatives and similar repositories for bapi-rv32i
Users that are interested in bapi-rv32i are comparing it to the libraries listed below
Sorting:
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated 2 months ago
- SoftCPU/SoC engine-V☆54Updated 5 months ago
- Naive Educational RISC V processor☆88Updated last month
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- ☆64Updated 6 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- A small 32-bit implementation of the RISC-V architecture☆32Updated 5 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆93Updated 5 years ago
- SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.☆32Updated 5 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Updated 2 years ago
- Small footprint and configurable SPI core☆42Updated last week
- Tiny tips for Colorlight i5 FPGA board☆57Updated 4 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆26Updated 5 years ago
- ☆19Updated 7 years ago
- A reimplementation of a tiny stack CPU☆85Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆62Updated 3 months ago
- Automated Git mirror of Gaisler's GRLIB/Leon3 releases☆20Updated 2 months ago
- Library of FPGA architectures☆24Updated this week
- AGM bitstream utilities and decoded files from Supra☆43Updated last month
- USB 1.1 Device IP Core☆21Updated 7 years ago
- RISC-V Configuration Structure☆41Updated 10 months ago
- Experiments with Yosys cxxrtl backend☆49Updated 7 months ago
- SD device emulator from ProjectVault☆17Updated 5 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago