lowRISC / riscv-compliance
TEMPORARY FORK of the riscv-compliance repository
☆16Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for riscv-compliance
- ☆37Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆59Updated 3 years ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 4 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆22Updated last month
- DUTH RISC-V Superscalar Microprocessor☆28Updated 3 weeks ago
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆63Updated 7 months ago
- ☆75Updated last year
- AXI Adapter(s) for RISC-V Atomic Operations☆58Updated 2 months ago
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆56Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- ☆25Updated 4 years ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆129Updated 2 weeks ago
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 8 months ago
- PCI Express controller model☆46Updated 2 years ago
- Platform Level Interrupt Controller☆35Updated 6 months ago
- StateMover is a checkpoint-based debugging framework for FPGAs.☆17Updated 2 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆29Updated 3 years ago
- General Purpose AXI Direct Memory Access☆44Updated 6 months ago
- RISC-V Verification Interface☆76Updated 2 months ago
- RISCV model for Verilator/FPGA targets☆45Updated 5 years ago
- ☆21Updated 2 months ago
- A Style Guide for the Chisel Hardware Construction Language☆106Updated 3 years ago
- Simple single-port AXI memory interface☆36Updated 5 months ago
- Original test vector of RISC-V Vector Extension☆11Updated 3 years ago
- [UNRELEASED] FP div/sqrt unit for transprecision☆18Updated 7 months ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆44Updated 3 years ago
- Archives of SystemC from The Ground Up Book Exercises☆28Updated 2 years ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆60Updated 6 months ago