Contains reference architecture scripts for running the OpenPiton regression using auto-scaling SLURM cluster.
☆23Feb 25, 2026Updated 5 months ago
Alternatives and similar repositories for eda-examples
Users that are interested in eda-examples are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MathLib DAC 2023 version☆13Sep 11, 2023Updated 2 years ago
- MPI Benchmark on AWS HPC cluster☆20Jan 31, 2020Updated 6 years ago
- Public repository to host our Checker IP written in SVA that is ported to run on open-source Verilator.☆12Mar 31, 2023Updated 3 years ago
- ☆11Jul 1, 2025Updated last year
- Samples and documentation for deploying EDA computing environments in AWS☆31Feb 6, 2026Updated 6 months ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- This repository contains sample code to help you extend your LSF cluster to the cloud. It provides fully functional examples of how to s…☆16Dec 17, 2025Updated 7 months ago
- ☆10Nov 2, 2023Updated 2 years ago
- 1-Click Cluster Deployment with AWS ParallelCluster☆30Sep 23, 2022Updated 3 years ago
- AI assisted Shell, aka "Ash". Wraps around your existing shell and brings AI-LLM to the CLI for analyzing EDA files.☆29Apr 6, 2026Updated 4 months ago
- APB UVC ported to Verilator☆11Nov 19, 2023Updated 2 years ago
- RTLMeter benchmark suite☆31Jul 21, 2026Updated 3 weeks ago
- ☆15May 24, 2025Updated last year
- A Lean-embedded framework to verify Verilog modules☆15Updated this week
- An opinionated build environment for EDA projects☆19Jul 20, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- SystemVerilog RTL Linter for YoSys☆24Nov 22, 2024Updated last year
- Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.☆27Mar 1, 2021Updated 5 years ago
- This repository is used to store CUDA-Q workshop material.☆17Jul 21, 2026Updated 3 weeks ago
- ☆14Apr 29, 2024Updated 2 years ago
- Microprobe: Microbenchmark generation framework☆27Feb 5, 2026Updated 6 months ago
- ICSE 2025: Fuzzing MLIR compilers with Custom Mutation Synthesis☆15Jul 22, 2025Updated last year
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Main repo for Go2UVM source code, examples and apps☆21Mar 31, 2023Updated 3 years ago
- ☆20Mar 1, 2021Updated 5 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Generic AXI interconnect fabric☆13Jul 17, 2014Updated 12 years ago
- An advanced automated reasoning tool for memory consistency model specifications.☆25Dec 6, 2021Updated 4 years ago
- ☆18Sep 2, 2020Updated 5 years ago
- ☆20Dec 29, 2014Updated 11 years ago
- A modular hardware abstraction library☆55Aug 3, 2026Updated last week
- Dynamic ControlFlow Graph and DataFlow Graph for Binary-based Optimization☆22Jul 5, 2017Updated 9 years ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 5 years ago
- ☆11Jun 29, 2021Updated 5 years ago
- Python library for parsing module definitions and instantiations from SystemVerilog files☆27Apr 29, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Support ThingShadow and MQTT protocol with Certificate Store by clientId (thingName)☆11Aug 24, 2020Updated 5 years ago
- RTLCheck☆26Oct 9, 2018Updated 7 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆39Jan 19, 2026Updated 6 months ago
- Open stadard cell library for open 28nm process☆17Jul 5, 2023Updated 3 years ago
- SystemVerilog Linter based on pyslang☆33May 5, 2025Updated last year
- Basic Common Modules☆48Jul 16, 2026Updated 3 weeks ago
- ☆19Oct 26, 2025Updated 9 months ago