riscv-non-isa / tg-nexus-traceView external linksLinks
RISC-V Nexus Trace TG documentation and reference code
☆57Feb 6, 2026Updated last week
Alternatives and similar repositories for tg-nexus-trace
Users that are interested in tg-nexus-trace are comparing it to the libraries listed below
Sorting:
- RISC-V Processor Trace Specification☆207Feb 9, 2026Updated last week
- A coverage library for Chisel designs☆11Mar 12, 2020Updated 5 years ago
- Capture retired instructions of a RISC-V Core and compress them to a sequence of packets.☆19Mar 13, 2024Updated last year
- RISC-V Processor Tracing tools and library☆16Mar 17, 2024Updated last year
- Coresight Wire Protocol (CSWP) Server/Client and streaming trace examples.☆28Jul 10, 2025Updated 7 months ago
- ☆18Sep 2, 2020Updated 5 years ago
- ☆20Mar 1, 2021Updated 4 years ago
- Simple UVM environment for experimenting with Verilator.☆28Nov 3, 2025Updated 3 months ago
- RISC-V Torture Test☆213Jul 11, 2024Updated last year
- Simple runtime for Pulp platforms☆51Feb 2, 2026Updated 2 weeks ago
- RTLMeter benchmark suite☆29Jan 25, 2026Updated 3 weeks ago
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- A gdbstub for connecting GDB to a RISC-V Debug Module☆30Oct 7, 2024Updated last year
- Instruction Set Generator initially contributed by Futurewei☆306Oct 17, 2023Updated 2 years ago
- Working Draft of the RISC-V Debug Specification Standard☆504Feb 5, 2026Updated last week
- ☆51Jan 9, 2026Updated last month
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated 10 months ago
- PLIC Specification☆150Feb 6, 2026Updated last week
- The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 …☆487Nov 27, 2025Updated 2 months ago
- RISC-V IOMMU Specification☆146Feb 8, 2026Updated last week
- ☆38Jul 9, 2024Updated last year
- ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…☆35Sep 30, 2020Updated 5 years ago
- Library of example SystemC/TLM peripherals for various SoCs based on the SCS library☆14Feb 8, 2026Updated last week
- ☆14Sep 14, 2020Updated 5 years ago
- RISC-V Debug Support for our PULP RISC-V Cores☆294Feb 4, 2026Updated 2 weeks ago
- An Open-Source Design and Verification Environment for RISC-V☆87Apr 21, 2021Updated 4 years ago
- ☆87Jan 30, 2026Updated 2 weeks ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆223Jan 11, 2026Updated last month
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 4 years ago
- GPU for OENG1167 in Verilog HDL for DE10 series boards☆15Nov 1, 2020Updated 5 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 9 years ago
- The RISC-V External Debug Security Specification☆20Feb 11, 2026Updated last week
- BFM Tester for Chisel HDL☆14Nov 27, 2021Updated 4 years ago
- ☆194Dec 14, 2023Updated 2 years ago
- ☆116Nov 11, 2025Updated 3 months ago
- ☆17Apr 3, 2022Updated 3 years ago
- CV32E40X Design-Verification environment☆16Mar 25, 2024Updated last year
- 🌄 RISC-V Ecosystem Landscape: a living document that developers, investors, vendors, researchers and others can use as a resource on the…☆21Updated this week
- Software, BSPs etc. for 5G wireless IP and PetaLinux☆20Dec 14, 2022Updated 3 years ago