AGM bitstream utilities and decoded files from Supra
☆48Aug 9, 2025Updated 6 months ago
Alternatives and similar repositories for rodinia
Users that are interested in rodinia are comparing it to the libraries listed below
Sorting:
- Load bitstream to AG1K series FPGA using CH552☆12Nov 19, 2021Updated 4 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 7 years ago
- AGRV2K裸奔测试工程☆29Jan 5, 2024Updated 2 years ago
- An attempt to reverse engineer a bitstream made for an AL3-10 FPGA☆16Jan 6, 2023Updated 3 years ago
- Documenting the Anlogic FPGA bit-stream format.☆88Dec 25, 2022Updated 3 years ago
- A low cost FPGA/CPLD dev-board based on AG1280Q48.☆73Jun 26, 2025Updated 8 months ago
- CKLink_Lite☆11Oct 18, 2021Updated 4 years ago
- Icarus SIMBUS☆20Nov 6, 2019Updated 6 years ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- STM32: example of usage of R820T2 tuner☆17Oct 29, 2018Updated 7 years ago
- USB-Blaster instance on CH55x MCU.☆57Jul 8, 2019Updated 6 years ago
- Example projects for Quokka FPGA toolkit☆37Jan 13, 2023Updated 3 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆23May 11, 2021Updated 4 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 7 years ago
- The program for USB-Blaster Chinese version on STM32 works with☆33Sep 7, 2017Updated 8 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Yosys plugin for logic locking and supply-chain security☆23Apr 5, 2025Updated 11 months ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated last year
- KLayout technology files for ASAP7 FinFET educational process☆25Feb 5, 2023Updated 3 years ago
- forked from https://github.com/riscv/riscv-openocd.git,and add falsh support for LicheeTang☆24Oct 18, 2021Updated 4 years ago
- A Verilog parser for Haskell.☆36Jul 6, 2021Updated 4 years ago
- Reference FPGA designs for interfacing with the internal ARM Cortex M3 MCU of the GW1NSR-4C, modified for use with boards like the Tang N…☆11Aug 13, 2022Updated 3 years ago
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Jan 18, 2021Updated 5 years ago
- Synthesiser for Asynchronous Verilog Language☆20Oct 29, 2014Updated 11 years ago
- A Linux rootkit☆10Nov 1, 2018Updated 7 years ago
- photonSDI - an open source SDI core☆10May 26, 2021Updated 4 years ago
- RISC-V 32-bit core for MCCI Catena 4710☆10Jul 31, 2019Updated 6 years ago
- 使用stm32f103系列实现的异步声卡,增加了CPLD外部时钟源(不再更新)☆11Feb 8, 2020Updated 6 years ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- Examples for Gowin Tang Nano 4k FPGA-board.☆13Aug 13, 2022Updated 3 years ago
- Sipeed Maix Uart Face Recognition Module/Firmware's Protocol Parse Library☆10Jun 5, 2019Updated 6 years ago
- ☆25Sep 27, 2018Updated 7 years ago
- ice40 UltraPlus demos☆23Oct 12, 2020Updated 5 years ago
- Single-chip solution for Hi-speed USB2.0(480Mbps) JTAG/SPI Debugger based on RISC-V MCU CH32V30x/CH32V20x☆122Jun 6, 2023Updated 2 years ago
- OpenGL 1.x implementation for FPGAs☆114Updated this week
- ☆16Jan 25, 2026Updated last month
- simple hyperram controller☆12Feb 10, 2019Updated 7 years ago
- ☆12Jun 4, 2021Updated 4 years ago
- Portable Event Library☆18Apr 28, 2025Updated 10 months ago