AGM bitstream utilities and decoded files from Supra
☆56Aug 9, 2025Updated last year
Alternatives and similar repositories for rodinia
Users that are interested in rodinia are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Load bitstream to AG1K series FPGA using CH552☆12Nov 19, 2021Updated 4 years ago
- An attempt to reverse engineer a bitstream made for an AL3-10 FPGA☆16Jan 6, 2023Updated 3 years ago
- Documenting the Anlogic FPGA bit-stream format.☆90Dec 25, 2022Updated 3 years ago
- A extremely size-optimized RV32I soft processor for FPGA.☆27Jun 19, 2018Updated 8 years ago
- AGRV2K裸奔测试工程☆30Jan 5, 2024Updated 2 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A low cost FPGA/CPLD dev-board based on AG1280Q48.☆74Jun 26, 2025Updated last year
- A Linux rootkit☆10Nov 1, 2018Updated 7 years ago
- CKLink_Lite☆12Oct 18, 2021Updated 4 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38May 7, 2024Updated 2 years ago
- HiLoTOF -- Hardware-in-the-Loop Test framework for Open FPGAs☆13Feb 9, 2019Updated 7 years ago
- The whole NFC solution (source code and schematic&layout) based on WCH chips☆49Jun 2, 2023Updated 3 years ago
- STM32: example of usage of R820T2 tuner☆17Oct 29, 2018Updated 7 years ago
- The program for USB-Blaster Chinese version on STM32 works with☆34Sep 7, 2017Updated 8 years ago
- ☆12Jun 4, 2021Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Apr 20, 2026Updated 3 months ago
- ☆73May 5, 2023Updated 3 years ago
- FPGA SDR platform: AD9963 + XC6SLX9 + CY7C68013☆18Jan 4, 2014Updated 12 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- MPSSE/JTAG impementation for the Raspberry Pi Pico☆15Mar 28, 2025Updated last year
- USB-Blaster instance on CH55x MCU.☆59Jul 8, 2019Updated 7 years ago
- Chisel Examples for the iCESugar FPGA Board☆12May 4, 2021Updated 5 years ago
- simple hyperram controller☆12Feb 10, 2019Updated 7 years ago
- 使用stm32f103系列实现的异步声卡，增加了CPLD外部时钟源（不再更新）☆11Feb 8, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆16Jan 25, 2026Updated 6 months ago
- Icarus SIMBUS☆21Nov 6, 2019Updated 6 years ago
- Yosys plugin for logic locking and supply-chain security☆24Apr 5, 2025Updated last year
- Ethernet MAC 10/100 Mbps☆39Oct 31, 2021Updated 4 years ago
- Enigma in FPGA☆29May 18, 2019Updated 7 years ago
- lightweight open HLS for FPGA rapid prototyping☆20Mar 22, 2018Updated 8 years ago
- forked from https://github.com/riscv/riscv-openocd.git,and add falsh support for LicheeTang☆24Oct 18, 2021Updated 4 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆24May 11, 2021Updated 5 years ago
- Winnermicro W60x Wi-Fi library reverse engineering notes & hackings☆20Nov 21, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- 串口通过9个元件转换为SWD接口☆14Feb 16, 2026Updated 5 months ago
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago
- FPGA 80186 IBM PC compatible system for Altera Cyclone IV (EP4CE15F23/EP4CE55F23)☆25Jan 15, 2022Updated 4 years ago
- ice40 UltraPlus demos☆23Oct 12, 2020Updated 5 years ago
- photonSDI - an open source SDI core☆11May 26, 2021Updated 5 years ago
- [MIGRATED to https://codeberg.org/prjunnamed/prjcombine/] An FPGA reverse engineering and documentation project☆65Mar 12, 2026Updated 5 months ago
- Python library for generating USB Descriptor byte strings using `struct` only.☆16Aug 13, 2021Updated 5 years ago