Alternatives and similar repositories for arl

Users that are interested in arl are comparing it to the libraries listed below

• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆75Updated 4 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆59Updated 9 years ago
• wudayemen / gen_apb_file
  ☆74Updated 4 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆73Updated 4 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆230Updated last year
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• ForrestBlue / cortexm0ds
  ☆69Updated 9 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆67Updated 5 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆104Updated 5 years ago
• microdynamics-cpu / tree-core-ide
  The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…
  ☆110Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆37Updated 10 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago
• WalkerLau / DetectHumanFaces
  Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
  ☆206Updated 2 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆54Updated 6 years ago
• CustomizableComputingLab / CustomizableComputingLab.github.io
  ☆149Updated last month
• cjhonlyone / NandFlashController
  AXI Interface Nand Flash Controller (Sync mode)
  ☆96Updated last year
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆222Updated 2 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆37Updated 5 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆141Updated last year
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• ljgibbslf / SM3_core
  ☆144Updated 5 years ago
• Frogwells / fpga_design
  这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
  ☆94Updated 8 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆67Updated last year
• freecores / round_robin_arbiter
  round robin arbiter
  ☆75Updated 11 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆163Updated 3 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• panicmarvin / cmsdk_ahb_busmatrix
  practice configure AHB-Lite bus protocol
  ☆14Updated 6 years ago