BitOpenFPGA / arl
lists of most popular repositories for most favoured programming languages (according to StackOverflow)
☆81Updated 4 years ago
Alternatives and similar repositories for arl:
Users that are interested in arl are comparing it to the libraries listed below
- Cortex M0 based SoC☆72Updated 3 years ago
- AXI DMA 32 / 64 bits☆111Updated 10 years ago
- ☆67Updated 3 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆68Updated 3 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆198Updated last year
- AXI总线连接器☆97Updated 5 years ago
- 视频旋转(2019FPGA大赛)☆33Updated 4 years ago
- ☆36Updated 9 years ago
- ☆131Updated 9 years ago
- FFT implement by verilog_测试验证已通过☆54Updated 8 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆64Updated 5 years ago
- Step by step tutorial for building CortexM0 SoC☆37Updated 3 years ago
- SDRAM controller with AXI4 interface☆90Updated 5 years ago
- FPGA 同步FIFO与异步FIFO☆30Updated 6 years ago
- Vivado诸多IP,包括图像处理等☆205Updated 8 months ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- Must-have verilog systemverilog modules☆33Updated 2 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆36Updated 8 years ago
- Gigabit Ethernet UDP communication driver☆75Updated 5 years ago
- ☆61Updated 9 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆39Updated 3 years ago
- upgrade to e203 (a risc-v core)☆41Updated 4 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆23Updated last year
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- SpinalHDL-tutorial based on Jupyter Notebook☆132Updated 10 months ago
- ☆143Updated last month
- DDR2 memory controller written in Verilog☆77Updated 13 years ago