Implement a bitonic sorting network on FPGA
☆48Nov 6, 2021Updated 4 years ago
Alternatives and similar repositories for SortingNetwork
Users that are interested in SortingNetwork are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆40Oct 4, 2024Updated last year
- 8b10b Encoder/Decoder☆13Jul 17, 2014Updated 11 years ago
- An open-source Xilinx Kria SOM Carrier for high-speed camera design☆31Dec 25, 2023Updated 2 years ago
- 使用verilog实现流水线 FFT☆15Jul 1, 2024Updated last year
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆34Aug 7, 2021Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆40May 11, 2021Updated 4 years ago
- P4_16 reference compiler☆23Dec 30, 2025Updated 3 months ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆18Aug 27, 2025Updated 7 months ago
- [ASP-DAC 2025] "NeuronQuant: Accurate and Efficient Post-Training Quantization for Spiking Neural Networks" Official Implementation☆19Mar 6, 2025Updated last year
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆47Jan 26, 2023Updated 3 years ago
- ☆37Jun 19, 2023Updated 2 years ago
- ☆12Nov 24, 2023Updated 2 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆16Aug 18, 2022Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board☆18Apr 13, 2022Updated 4 years ago
- Chisel NVMe controller☆27Nov 24, 2022Updated 3 years ago
- A simulation framework for modeling efficiency of Graph Neural Network Dataflows☆24Feb 14, 2025Updated last year
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- Ethernet switch implementation written in Verilog☆63Jun 13, 2023Updated 2 years ago
- ☆17Sep 6, 2024Updated last year
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆142Jan 26, 2024Updated 2 years ago
- ☆12May 5, 2015Updated 10 years ago
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆42Jan 12, 2016Updated 10 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆32Apr 25, 2016Updated 9 years ago
- the xoroshiro32++ and xoroshiro64++ PRNG algorthims by David Blackman and Sebastiano Vigna in C++, Verilog, VHDL and SpinalHDL.☆16Dec 2, 2018Updated 7 years ago
- Robust CFAR detector based on censored harmonic averaging☆11Sep 1, 2023Updated 2 years ago
- ☆21Mar 18, 2022Updated 4 years ago
- MATLAB Vision HDL☆16Jan 17, 2020Updated 6 years ago
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- 大三上做的本科毕设,包含BNN的替代梯度训练,verilog电路实现,完成180nm工艺流片。☆23Jun 30, 2025Updated 9 months ago
- Hardware Division Units☆10Jul 17, 2014Updated 11 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆73Aug 30, 2022Updated 3 years ago
- ☆19Dec 19, 2018Updated 7 years ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆60Nov 22, 2023Updated 2 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- GPGPU-SIM 使用篇☆14Nov 12, 2022Updated 3 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆12Apr 26, 2022Updated 3 years ago