Alternatives and similar repositories for ADC_Sigma_Delta_VHDL

Users that are interested in ADC_Sigma_Delta_VHDL are comparing it to the libraries listed below

• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆13Updated 7 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆45Updated 5 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆29Updated 5 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆92Updated 5 years ago
• r09g / iadc
  12-bit 10-KSPS Incremental Delta-Sigma ADC in Skywater 130 nm
  ☆20Updated 2 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆61Updated 6 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 8 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆37Updated 6 years ago
• tgingold / OpenTDC
  Time to Digital Converter (TDC)
  ☆31Updated 4 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆27Updated 3 years ago
• Cognoscan / VerilogCogs
  Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
  ☆20Updated 10 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆40Updated 5 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆43Updated 4 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 8 years ago
• freecores / wb_builder
  WISHBONE Builder
  ☆15Updated 8 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆68Updated 7 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆67Updated 7 months ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆24Updated 3 years ago
• freecores / usb_phy
  USB 1.1 PHY
  ☆11Updated 11 years ago
• TUT-ASI / leon3-grlib-gpl-mirror
  Automated Git mirror of Gaisler's GRLIB/Leon3 releases
  ☆19Updated last month
• HarmonInstruments / verilog
  ☆20Updated 3 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 6 months ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆91Updated 7 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆26Updated 4 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆52Updated 9 months ago
• Featherweight-IP / fwrisc
  Featherweight RISC-V implementation
  ☆53Updated 3 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆23Updated 9 years ago