Alternatives and similar repositories for iic-audiodac-v1

Users that are interested in iic-audiodac-v1 are comparing it to the libraries listed below

• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• iic-jku / osic-multitool
  JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
  ☆67Updated 4 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆66Updated 2 years ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆64Updated last month
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆44Updated 3 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆73Updated 4 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆36Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆72Updated last month
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆53Updated last year
• iic-jku / Circuit-Designers-Etiquette
  A set of rules and recommendations for analog and digital circuit designers.
  ☆28Updated 9 months ago
• praharshapm / vsdmixedsignalflow
  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…
  ☆44Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆58Updated 2 years ago
• bluecmd / learn-sky130
  Learning to do things with the Skywater 130nm process
  ☆84Updated 4 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆114Updated 4 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆73Updated 4 years ago
• UAH-IC-Design-Team / sky130-10-bit-SAR-ADC
  A 10bit SAR ADC in Sky130
  ☆25Updated 2 years ago
• shariethernet / Physical-Design-with-OpenLANE-using-SKY130-PDK
  This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…
  ☆46Updated 4 years ago
• IHP-GmbH / IHP-AnalogAcademy
  ☆85Updated 2 weeks ago
• mabrains / PLL_design
  PLL Designs on Skywater 130nm MPW
  ☆20Updated last year
• sscs-ose / sscs-chipathon-2024
  ☆84Updated 6 months ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆108Updated last year
• efabless / chipignite-resources
  ☆81Updated 2 years ago
• mabrains / OpenAnalogDesign
  Open Analog Design Environment
  ☆24Updated 2 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• akshaymdas / OpenLANE-SkyWater130-workshop
  This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…
  ☆22Updated 4 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆31Updated 4 years ago
• wallento / cocotbext-wishbone
  ☆14Updated 8 months ago
• ShonTaware / OpenSource_Physical_Design
  This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK
  ☆38Updated 3 years ago
• Akash-Perla / ASIC-Design
  This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)
  ☆13Updated 8 months ago