Alternatives and similar repositories for matchlib_toolkit

Users that are interested in matchlib_toolkit are comparing it to the libraries listed below

• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆25Updated 7 months ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆42Updated last month
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆62Updated 5 months ago
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆105Updated last week
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 5 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆38Updated 3 weeks ago
• AndrewNolte / vscode-system-verilog
  SystemVerilog/Verilog support for vscode
  ☆29Updated 2 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆110Updated last year
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆21Updated 7 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆95Updated last week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆169Updated 3 weeks ago
• pulp-platform / redmule
  ☆68Updated this week
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆35Updated 4 years ago
• amin-norollah / PAT-Noxim
  cycle accurate Network-on-Chip Simulator
  ☆28Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆57Updated 3 years ago
• The-OpenROAD-Project / megaboom
  ☆27Updated last week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆112Updated last year
• cornell-brg / pymtl3-net
  Project repo for the POSH on-chip network generator
  ☆48Updated 4 months ago
• Jerc007 / Open-GPGPU-FlexGrip-
  FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
  ☆106Updated 2 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆59Updated 5 years ago
• hossein1387 / BARVINN
  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
  ☆90Updated 6 months ago
• pulp-platform / axi_mem_if
  Simple single-port AXI memory interface
  ☆42Updated last year
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆42Updated 2 years ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆97Updated last month
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆13Updated last week
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆38Updated 6 months ago
• tomverbeure / math
  SpinalHDL Hardware Math Library
  ☆88Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆29Updated last month
• StanfordAHA / garnet
  Next generation CGRA generator
  ☆112Updated this week
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago