Alternatives and similar repositories for riscv-gdbserver

Users that are interested in riscv-gdbserver are comparing it to the libraries listed below

• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆30Updated last year
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• openrisc / or1ksim
  The OpenRISC 1000 architectural simulator
  ☆77Updated 9 months ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆64Updated 4 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆107Updated 4 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆55Updated 10 months ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆107Updated 11 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆91Updated 5 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆72Updated 7 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆39Updated 2 years ago
• freecores / sparc64soc
  OpenSPARC-based SoC
  ☆75Updated 11 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 6 years ago
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆17Updated 13 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated last year
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆53Updated 4 years ago
• pulp-platform / trdb
  RISC-V processor tracing tools and library
  ☆16Updated last year
• riscv / riscv-test-env
  ☆51Updated 3 weeks ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆51Updated 10 months ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• himanshu5-prog / vortexGPU
  ☆24Updated 4 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• ecilasun / NekoIchi
  A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board
  ☆33Updated 4 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆34Updated last year
• ultraembedded / core_mmc
  MMC (and derivative standards) host controller
  ☆25Updated 5 years ago
• fjullien / jtag_vpi
  TCP/IP controlled VPI JTAG Interface.
  ☆69Updated last year
• b224hisl / rioschip
  ☆33Updated 3 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆45Updated 8 years ago
• s094392 / riscv-bare-metal
  A RISC-V bare metal example
  ☆54Updated 3 years ago