jhoecmu / ooo-betaView external linksLinks
☆12Aug 12, 2022Updated 3 years ago
Alternatives and similar repositories for ooo-beta
Users that are interested in ooo-beta are comparing it to the libraries listed below
Sorting:
- A repository for FAQs regarding the 18240 class.☆11Jan 21, 2026Updated 3 weeks ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆15Updated this week
- Complete tutorial code.☆23Apr 29, 2024Updated last year
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- Simulator for a superscalar processor with dynamic scheduling and branch prediction☆15Nov 23, 2018Updated 7 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- 经典的嵌入式OS - ucos-II 2.52版本全注释,仅供学习交流使用。☆12Oct 16, 2019Updated 6 years ago
- RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga☆14Feb 26, 2025Updated 11 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆50Feb 26, 2025Updated 11 months ago
- livecoding talk for oscon 2018☆10Jul 18, 2018Updated 7 years ago
- ☆11Sep 25, 2021Updated 4 years ago
- Works for Applied Deep Learning / Machine Learning and Having It Deep and Structured (2017 FALL) @ NTU☆11Aug 14, 2018Updated 7 years ago
- A docker image for One Student One Chip's debug exam☆10Sep 22, 2023Updated 2 years ago
- Linux porting to NonTrivialMIPS (based on linux-stable)☆12Aug 17, 2019Updated 6 years ago
- simple 4-BIT CPU with 74-serials chip,origin by Kaoru Tonami in his book “How to build a CPU”☆14Oct 19, 2024Updated last year
- Verilog code of Loongson's GS132 core☆12Dec 19, 2019Updated 6 years ago
- A Flexible Cache Architectural Simulator☆16Sep 16, 2025Updated 4 months ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆20Nov 9, 2025Updated 3 months ago
- This repo is for the Linkedin Learning course: Training Neural Networks in C++☆11Oct 24, 2023Updated 2 years ago
- Explore the behavior SystemC kernel event-driven simulator (aka "the engine")☆11Jan 17, 2024Updated 2 years ago
- FPGA Labs for EECS 151/251A (Fall 2021)☆11Oct 20, 2021Updated 4 years ago
- ☆13May 8, 2025Updated 9 months ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆21Apr 25, 2025Updated 9 months ago
- Running ahead of memory latency - Part II project☆10Jan 7, 2023Updated 3 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆54Mar 24, 2024Updated last year
- A virtio layer for xv6☆12Apr 16, 2019Updated 6 years ago
- ☆16Jan 18, 2025Updated last year
- ☆15Dec 17, 2025Updated last month
- Architect's workbench☆10May 5, 2016Updated 9 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆24Updated this week
- CMU Courses☆15Dec 26, 2025Updated last month
- ☆12Feb 6, 2026Updated last week
- SystemVerilog implemention of the TAGE branch predictor☆13May 26, 2021Updated 4 years ago
- Lower chisel memories to SRAM macros☆13Mar 25, 2024Updated last year
- Vivado in GitLab-Runner for GitLab CI/CD☆10Oct 27, 2022Updated 3 years ago
- Deep learning algorithms developed by ourselves from scratch by C++. No deep learning frameworks are used.☆10Aug 3, 2020Updated 5 years ago
- Digital system design: Training lessons and exercise projects for students☆11May 12, 2023Updated 2 years ago
- Sifive All Aboard 系列文章翻译☆11Nov 26, 2021Updated 4 years ago
- Simple PyTorch profiler that combines DeepSpeed Flops Profiler and TorchInfo☆11Feb 12, 2023Updated 3 years ago