pulp-platform / pulp-trainlibLinks
Floating-Point Optimized On-Device Learning Library for the PULP Platform.
☆36Updated this week
Alternatives and similar repositories for pulp-trainlib
Users that are interested in pulp-trainlib are comparing it to the libraries listed below
Sorting:
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆86Updated 3 months ago
- ☆47Updated 4 months ago
- NeuraLUT-Assemble☆38Updated this week
- DNN Compiler for Heterogeneous SoCs☆44Updated last week
- ☆63Updated 3 months ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆83Updated 3 weeks ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆156Updated last month
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆58Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆56Updated 10 months ago
- ☆72Updated 2 weeks ago
- ☆26Updated last week
- A collection of tutorials for the fpgaConvNet framework.☆44Updated 11 months ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆150Updated this week
- FPGA based Vision Transformer accelerator (Harvard CS205)☆126Updated 6 months ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆53Updated last year
- Machine-Learning Accelerator System Exploration Tools☆173Updated 2 months ago
- PyTorch model to RTL flow for low latency inference☆131Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆39Updated last week
- muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.☆85Updated last week
- A DSL for Systolic Arrays☆80Updated 6 years ago
- ☆58Updated 5 years ago
- ☆83Updated last year
- BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/☆90Updated 7 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 3 years ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆30Updated 11 months ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆37Updated 5 months ago
- Resource Utilization and Latency Estimation for ML on FPGA.☆15Updated last month
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆30Updated 9 months ago