Floating-Point Optimized On-Device Learning Library for the PULP Platform.
☆41Mar 3, 2026Updated 3 months ago
Alternatives and similar repositories for pulp-trainlib
Users that are interested in pulp-trainlib are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Neural Engine, 16 input channels☆16Oct 31, 2022Updated 3 years ago
- Driving Snax with MLIR☆21Apr 22, 2026Updated 2 months ago
- ☆41Mar 5, 2024Updated 2 years ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆22Nov 9, 2025Updated 7 months ago
- ☆11Sep 3, 2022Updated 3 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Brainchip Akida Neuromorphic System-on-Chip examples and documentation.☆32May 21, 2026Updated last month
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆94Aug 4, 2025Updated 10 months ago
- NEural Minimizer for pytOrch☆47Jul 25, 2024Updated last year
- ☆24Apr 17, 2026Updated 2 months ago
- The EEMBC EnergyRunner application framework for the MLPerf Tiny benchmark.☆22Apr 16, 2023Updated 3 years ago
- ☆27Jan 30, 2026Updated 5 months ago
- Simple UVM environment for experimenting with Verilator.☆39Apr 29, 2026Updated 2 months ago
- DNN Compiler for Heterogeneous SoCs☆70Jun 23, 2026Updated last week
- Neuromorphic simulator with two modes of computation☆13Mar 4, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This repository contains low-bit quantization papers from 2020 to 2026 on top conference.☆174Updated this week
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆127Jun 11, 2026Updated 2 weeks ago
- ☆15Dec 8, 2025Updated 6 months ago
- ☆19Apr 29, 2025Updated last year
- Pulp virtual platform☆24Jul 16, 2025Updated 11 months ago
- HW accelerator mapping optimization framework for in-memory computing☆30Jun 3, 2025Updated last year
- All things related to cMIPS, a synthesizable VHDL model for the 5-stage pipeline, MIPS32r2 core.☆13Jun 8, 2019Updated 7 years ago
- Vstream - Video Analytics pipeline with Hardware based accelerations (dev - stage)☆10Feb 2, 2024Updated 2 years ago
- Source code for the architectural and circuit-level simulators used for modeling the CROW (Copy-ROW DRAM) mechanism proposed in our ISCA …☆16Aug 2, 2019Updated 6 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- RISC-V fast interrupt controller☆35Jun 8, 2026Updated 3 weeks ago
- Chameleon: A Multiplier-Free Temporal Convolutional Network Accelerator for End-to-End Few-Shot and Continual Learning from Sequential Da…☆27Mar 5, 2026Updated 3 months ago
- DINC is a framework that efficiently plans and implements P4-based service partitions on multiple network devices.☆30Feb 10, 2026Updated 4 months ago
- Deep and online learning with spiking neural networks in Python for Graphcore IPU☆10Apr 8, 2023Updated 3 years ago
- DMA Hardware Description with Verilog☆20Dec 20, 2019Updated 6 years ago
- This is the repository containing the implementation of sparse dense matrix multiplication for the matrix dimension of 560 x 560.☆10Jul 7, 2021Updated 4 years ago
- Petri Net Simulator program☆10Nov 27, 2017Updated 8 years ago
- UVM/systemverilog/verilog/python VIM IDE☆17Aug 21, 2013Updated 12 years ago
- Linux on RISC-V on FPGA (LOROF): RV64GC Sv39 Quad-Core Superscalar Out-of-Order Virtual Memory CPU☆17Updated this week
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Mar 29, 2024Updated 2 years ago
- Simodense: a RISC-V softcore for custom SIMD instructions☆17Feb 16, 2026Updated 4 months ago
- ☆16Sep 27, 2023Updated 2 years ago
- ☆126Apr 20, 2026Updated 2 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆68Jun 18, 2026Updated last week
- ☆28Aug 28, 2024Updated last year
- Optimizing the Deployment of Tiny Transformers on Low-Power MCUs☆38Sep 2, 2024Updated last year