eml-eda / messyLinks
Messy is an open-source framework that integrates a RISC-V ISS with SystemC-AMS
☆20Updated 3 months ago
Alternatives and similar repositories for messy
Users that are interested in messy are comparing it to the libraries listed below
Sorting:
- A tool to deploy Deep Neural Networks on PULP-based SoC's☆91Updated 4 months ago
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆175Updated 2 months ago
- Efficient Decision tree Ensembles library for IoT edge nodes☆16Updated 11 months ago
- DNN Compiler for Heterogeneous SoCs☆59Updated this week
- An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs☆56Updated 4 months ago
- ☆78Updated 3 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆162Updated this week
- NeuraLUT-Assemble☆46Updated 4 months ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆64Updated 5 months ago
- ☆53Updated 5 months ago
- gem5-X open source project☆18Updated 2 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆101Updated 2 weeks ago
- A fast, accurate trace-based simulator for High-Level Synthesis.☆73Updated last week
- Floating-Point Optimized On-Device Learning Library for the PULP Platform.☆37Updated 2 weeks ago
- Algorithmic C Machine Learning Library☆26Updated last month
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆56Updated last year
- A survey on Hardware Accelerated LLMs☆60Updated 11 months ago
- Train and deploy LUT-based neural networks on FPGAs☆109Updated last year
- Resource Utilization and Latency Estimation for ML on FPGA.☆17Updated 3 months ago
- Machine-Learning Accelerator System Exploration Tools☆183Updated last week
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆73Updated last month
- An Open-Hardware CGRA for accelerated computation on the edge.☆39Updated last month
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆69Updated 3 months ago
- A scalable High-Level Synthesis framework on MLIR☆285Updated last year
- ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference☆179Updated 3 weeks ago
- PyTorch model to RTL flow for low latency inference☆131Updated last year
- Network on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator☆36Updated 2 years ago
- An Open-Source Tool for CGRA Accelerators☆80Updated 3 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 10 months ago
- ☆12Updated 8 months ago