Alternatives and similar repositories for messy

Users that are interested in messy are comparing it to the libraries listed below

• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆158Updated last month
• eml-eda / eden
  Efficient Decision tree Ensembles library for IoT edge nodes
  ☆16Updated 7 months ago
• pulp-platform / dory
  A tool to deploy Deep Neural Networks on PULP-based SoC's
  ☆88Updated last month
• MartaAndronic / NeuraLUT
  NeuraLUT-Assemble
  ☆41Updated last month
• pulp-platform / pulp-trainlib
  Floating-Point Optimized On-Device Learning Library for the PULP Platform.
  ☆36Updated last month
• DeepWok / mase
  Machine-Learning Accelerator System Exploration Tools
  ☆178Updated this week
• UCLA-VAST / Stream-HLS
  An MLIR Complier for PyTorch/C/C++ Codes into HLS Dataflow Designs
  ☆47Updated last month
• maeri-project / FEATHER
  A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching
  ☆63Updated last month
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆155Updated this week
• mit-emze / cimloop
  ☆66Updated last month
• pulp-platform / Deeploy
  DNN Compiler for Heterogeneous SoCs
  ☆47Updated last week
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆58Updated 2 months ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆89Updated this week
• Accelergy-Project / timeloop-accelergy-exercises
  Exercises for exploring the Fibertree, Timeloop and Accelergy tools
  ☆104Updated 5 months ago
• Xilinx / logicnets
  Train and deploy LUT-based neural networks on FPGAs
  ☆98Updated last year
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆69Updated 6 months ago
• Accelergy-Project / accelergy
  Accelergy is an energy estimation infrastructure for accelerator energy estimations
  ☆149Updated 4 months ago
• MartaAndronic / PolyLUT
  PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…
  ☆53Updated last year
• IMPETUS-UdeS / rule4ml
  Resource Utilization and Latency Estimation for ML on FPGA.
  ☆15Updated this week
• pnnl / soda-opt
  ☆49Updated 2 months ago
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆64Updated 6 months ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆131Updated last year
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆130Updated 7 months ago
• KULeuven-MICAS / DeFiNES
  A framework for fast exploration of the depth-first scheduling space for DNN accelerators
  ☆40Updated 2 years ago
• robertoBosio / NN2FPGA
  From Pytorch model to C++ for Vitis HLS
  ☆17Updated last week
• awai54st / LUTNet
  ☆60Updated 5 years ago
• ebby-s / MX-for-FPGA
  Implementation of Microscaling data formats in SystemVerilog.
  ☆24Updated 2 months ago
• Accelergy-Project / accelergy-timeloop-infrastructure
  Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop
  ☆57Updated 5 months ago
• stonne-simulator / stonne
  STONNE: A Simulation Tool for Neural Networks Engines
  ☆138Updated 3 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆80Updated 3 years ago