Alternatives and similar repositories for bao-cva6-guide

Users that are interested in bao-cva6-guide are comparing it to the libraries listed below

• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆44Updated 7 months ago
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆103Updated 6 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆128Updated last week
• riscv-ovpsim / imperas-riscv-tests
  ☆187Updated last year
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 2 months ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆146Updated 2 weeks ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆196Updated last year
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆214Updated 6 months ago
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆187Updated last week
• riscvarchive / riscv-CMOs
  ☆90Updated 2 weeks ago
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆33Updated last week
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆255Updated 3 months ago
• riscv / riscv-aia
  ☆95Updated 2 weeks ago
• riscv-software-src / riscof
  ☆90Updated 2 weeks ago
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆177Updated 9 months ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆165Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆293Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated last month
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆270Updated 4 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆244Updated 2 years ago
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆218Updated 3 months ago
• mariusmm / RISC-V-TLM
  RISC-V SystemC-TLM simulator
  ☆320Updated 8 months ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• chipsalliance / uvm-verilator
  ☆97Updated last year
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆297Updated 2 weeks ago
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆102Updated 3 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆159Updated 3 weeks ago