Alternatives and similar repositories for bao-cva6-guide

Users that are interested in bao-cva6-guide are comparing it to the libraries listed below

• zero-day-labs / riscv-aia
  AIA IP compliant with the RISC-V AIA spec
  ☆42Updated 6 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆71Updated last month
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆102Updated 6 years ago
• riscv-non-isa / riscv-iommu
  RISC-V IOMMU Specification
  ☆125Updated this week
• riscv / riscv-CMOs
  ☆89Updated 3 years ago
• riscv-ovpsim / imperas-riscv-tests
  ☆182Updated last year
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆195Updated last year
• riscv-non-isa / iopmp-spec
  This repository contains the specification source for the RISC-V IOPMP Specification. This document proposes a Physical Memory Protectio…
  ☆30Updated last week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆172Updated 7 months ago
• riscv / riscv-aia
  ☆92Updated this week
• riscvarchive / riscv-aclint
  ☆42Updated 3 years ago
• riscv / riscv-plic-spec
  PLIC Specification
  ☆144Updated 2 years ago
• mathis-s / SoomRV
  A simple superscalar out-of-order RISC-V microprocessor
  ☆211Updated 5 months ago
• chipsalliance / uvm-verilator
  ☆97Updated last year
• litmus-tests / litmus-tests-riscv
  RISC-V architecture concurrency model litmus tests
  ☆83Updated 2 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆69Updated last year
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆89Updated 2 weeks ago
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 8 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆101Updated this week
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆141Updated 5 years ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• riscv-software-src / riscv-perf-model
  Example RISC-V Out-of-Order/Superscalar Processor Performance Core and MSS Model
  ☆183Updated this week
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆99Updated 2 months ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated this week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆290Updated last year
• riscv-software-src / riscof
  ☆84Updated 4 months ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆66Updated 6 years ago
• riscvarchive / riscv-eabi-spec
  Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.
  ☆27Updated 4 years ago
• Xilinx / libsystemctlm-soc
  SystemC/TLM-2.0 Co-simulation framework
  ☆252Updated 2 months ago