CTSRD-CHERI / cheri-specificationLinks
CHERI ISA Specification
☆24Updated this week
Alternatives and similar repositories for cheri-specification
Users that are interested in cheri-specification are comparing it to the libraries listed below
Sorting:
- A tool to enable fuzzing for Spectre vulnerabilities☆31Updated 5 years ago
- A tool for detecting Spectre vulnerabilities through fuzzing☆44Updated 4 years ago
- HW interface for memory caches☆28Updated 5 years ago
- ☆45Updated 6 years ago
- Artifact of "Indirector: High-Precision Branch Target Injection Attacks Exploiting the Indirect Branch Predictor" [USENIX Security 2024]☆63Updated last year
- Proof-of-concept implementation for the paper "Osiris: Automated Discovery of Microarchitectural Side Channels" (USENIX Security'21)☆60Updated 4 months ago
- QEMU with support for CHERI☆61Updated last week
- Revizor - a fuzzer to search for microarchitectural leaks in CPUs☆162Updated last week
- Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆20Updated 3 years ago
- RISC-V Tools (GNU Toolchain, ISA Simulator, Tests)☆21Updated 6 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆22Updated 3 years ago
- Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser☆62Updated 3 years ago
- RISC-V Security Model☆32Updated this week
- ☆16Updated 10 months ago
- Medusa Repository: Transynther tool and Medusa Attack☆23Updated 5 years ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆37Updated 3 years ago
- Kasper: Scanning for Generalized Transient Execution Gadgets in the Linux Kernel☆58Updated last year
- Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor☆20Updated last year
- some tlb experimentation code: calculate L1, L2 miss penalties and show cross-HT interference.☆14Updated 6 years ago
- ☆18Updated 3 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆26Updated 3 months ago
- Artifacts for Cascade: CPU Fuzzing via Intricate Program Generation (USENIX Security 2024)☆135Updated last year
- Artifact evaluation of paper: MorFuzz: Fuzzing Processor via Runtime Instruction Morphing enhanced Synchronizable Co-simulation☆45Updated 5 months ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆71Updated 6 months ago
- Proof-of-concept for I See Dead Micro-Ops transient execution attack☆14Updated 3 years ago
- Microarchitectural exploitation and other hardware attacks.☆96Updated last year
- ☆95Updated last year
- Using Malicious #VC Interrupts to Break AMD SEV-SNP (IEEE S&P 2024)☆24Updated last year
- ☆27Updated last year
- Memory Tagging ISA extension that can be used by software to enforce memory tag checks on memory loads and stores☆22Updated 2 weeks ago