Alternatives and similar repositories for iopmp

Users that are interested in iopmp are comparing it to the libraries listed below

• riscv-admin / trusted-computing
  ☆23Updated 2 years ago
• riscv-non-isa / riscv-ap-tee
  This repo holds the work area and revisions of the non-ISA specification created by the RISC-V AP-TEE TG. This specification defines the …
  ☆65Updated last month
• riscvarchive / riscv-tee
  ☆38Updated 3 years ago
• riscv / riscv-spmp
  The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by…
  ☆21Updated last month
• riscvarchive / security
  RISC-V Security HC admin repo
  ☆18Updated last year
• ilebedev / sanctum
  The MIT Sanctum processor top-level project
  ☆31Updated 5 years ago
• rivosinc / salus
  Risc-V hypervisor for TEE development
  ☆126Updated 2 weeks ago
• larkmjc / rv8-bench
  rv8 benchmark suite
  ☆23Updated 5 years ago
• Penglai-Enclave / Penglai-Enclave
  This is the main repo for Penglai.
  ☆73Updated 2 years ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆28Updated 7 months ago
• Penglai-Enclave / Penglai-Enclave-TVM
  The main repo of Penglai Enclave based on RISC-V Trapped Virtual Memory (TVM).
  ☆41Updated 2 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 4 months ago
• riscv / riscv-smmtt
  This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…
  ☆64Updated 2 weeks ago
• jasonyu1996 / elasticlave
  ☆28Updated 10 months ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆17Updated 4 years ago
• Compass-All / Raft
  Hardware-assisted Dynamic Information Flow Tracking for Runtime Protection on RISC-V
  ☆11Updated 2 years ago
• riscv-non-isa / riscv-security-model
  RISC-V Security Model
  ☆34Updated last month
• TF-RMM / tf-rmm
  Reference implementation of Arm-CCA RMM specification
  ☆70Updated this week
• TwinVisor / twinvisor-prototype
  ☆22Updated 3 years ago
• riscv-admin / uarch-side-channels
  ☆16Updated last year
• proteus-core / prospect
  ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
  ☆19Updated 5 months ago
• dskarlatos / MicroScope
  Microscope: Enabling Microarchitectural Replay Attacks
  ☆20Updated 5 years ago
• ccc-spdm-tools / spdm-rs
  A rust implementation for DMTF SPDM protocol to support Confidential Computing
  ☆49Updated last week
• sectrs-acai / acai
  Protecting Accelerator Execution with Arm Confidential Computing Architecture (USENIX Security 2024)
  ☆26Updated 2 years ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated 2 years ago
• Penglai-Enclave / Penglai-Enclave-sPMP
  Penglai Enclave is an open-sourced, secure and scalable TEE system for RISC-V.
  ☆146Updated 10 months ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆77Updated 2 months ago
• efeslab / dolma
  ☆14Updated 4 years ago
• ESCristiano / BUSted
  BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect
  ☆11Updated last year