marcoz001 / axi-uvmLinks
yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
☆120Updated 7 years ago
Alternatives and similar repositories for axi-uvm
Users that are interested in axi-uvm are comparing it to the libraries listed below
Sorting:
- UVM AHB VIP☆86Updated 7 months ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆151Updated 5 years ago
- UVM examples and projects☆140Updated 6 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆172Updated 6 years ago
- VIP for AXI Protocol☆137Updated 3 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆91Updated last year
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆143Updated 6 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆104Updated 5 months ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆40Updated 5 years ago
- This is the main repository for all the examples for the book Practical UVM☆196Updated 4 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆101Updated 7 years ago
- uvm AXI BFM(bus functional model)☆248Updated 12 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- Verification IP for APB protocol☆66Updated 4 years ago
- SystemVerilog VIP for AMBA APB protocol☆75Updated 3 years ago
- An uvm verification env for ahb2apb bridge☆53Updated 4 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆52Updated 4 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆102Updated 11 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆31Updated 4 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆207Updated last year
- a very simple risc_cpu verification demo with uvm☆24Updated 6 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- Yet Another Simulation Architecture☆73Updated 4 years ago
- Verification IP for I2C protocol☆46Updated 3 years ago
- ☆40Updated last year
- AHB to APB Bridge VIP☆29Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago