marcoz001 / axi-uvm

Related projects ⓘ

Alternatives and complementary repositories for axi-uvm

• seabeam / yuu_ahb
  UVM AHB VIP
  ☆77Updated 2 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆147Updated 4 years ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆108Updated 2 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆121Updated 5 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆154Updated 6 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆93Updated 6 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆129Updated 6 years ago
• Siddhi-95 / AHB-to-APB-Bridge-Verification
  Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.
  ☆71Updated last year
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆111Updated 3 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆36Updated 3 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆34Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆172Updated 4 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆89Updated 6 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆67Updated 3 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆54Updated last year
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆22Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆100Updated 10 years ago
• naragece / uvm-testbench-tutorial-simple-adder
  A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology
  ☆93Updated 10 years ago
• VerificationExcellence / SystemVerilogAssertions
  Examples and reference for System Verilog Assertions
  ☆81Updated 7 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆47Updated 3 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆56Updated 3 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆233Updated 11 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆49Updated 2 years ago
• akzare / Async_FIFO_Verification
  Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.
  ☆47Updated 4 years ago
• Anjali-287 / SPI-Interface
  UVM Testbench to verify serial transmission of data between SPI master and slave
  ☆34Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆51Updated 7 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆37Updated 4 years ago
• kkenshin1 / AXI-Ethernet-UVM
  A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM
  ☆20Updated 2 years ago
• dovstamler / uvm_agents
  UVM agents
  ☆74Updated 7 years ago