yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
☆135Nov 29, 2017Updated 8 years ago
Alternatives and similar repositories for axi-uvm
Users that are interested in axi-uvm are comparing it to the libraries listed below
Sorting:
- AMBA AXI VIP☆448Jun 28, 2024Updated last year
- uvm AXI BFM(bus functional model)☆266Jun 23, 2013Updated 12 years ago
- UVM AHB VIP☆93Sep 13, 2025Updated 5 months ago
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆21Feb 7, 2025Updated last year
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆160Jul 16, 2018Updated 7 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆117Nov 27, 2017Updated 8 years ago
- Verification IP for I2C protocol☆52Sep 22, 2021Updated 4 years ago
- Verification IP for APB protocol☆73Dec 18, 2020Updated 5 years ago
- This is the main repository for all the examples for the book Practical UVM☆216Oct 21, 2020Updated 5 years ago
- UVM examples and projects☆155Jun 28, 2025Updated 8 months ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆28Mar 26, 2017Updated 8 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆31Jun 1, 2022Updated 3 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆191Jul 23, 2018Updated 7 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Apr 7, 2018Updated 7 years ago
- amba3 apb/axi vip☆53Feb 24, 2015Updated 11 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆35Feb 28, 2026Updated last week
- DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision☆75Mar 21, 2024Updated last year
- A simple UVM example with DPI☆45Aug 7, 2017Updated 8 years ago
- VIP for AXI Protocol☆164May 24, 2022Updated 3 years ago
- Awesome ASIC design verification☆343Feb 9, 2022Updated 4 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆159Mar 31, 2020Updated 5 years ago
- ☆27May 11, 2021Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 5 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆106Jul 2, 2023Updated 2 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆65Oct 19, 2023Updated 2 years ago
- Novel GUI Based UVM Testbench Template Builder☆150Apr 14, 2021Updated 4 years ago
- Maven Silicon Project☆20Oct 13, 2018Updated 7 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆119Dec 29, 2024Updated last year
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆11Aug 21, 2023Updated 2 years ago
- Reference examples and short projects using UVM Methodology☆291May 18, 2022Updated 3 years ago
- AXI总线连接器☆105Mar 26, 2020Updated 5 years ago
- my UVM training projects☆39Mar 14, 2019Updated 6 years ago
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- UVM VIP architecture generator☆20Aug 24, 2020Updated 5 years ago
- ☆21Feb 20, 2026Updated 2 weeks ago
- AXI4 and AXI4-Lite interface definitions☆102Sep 20, 2020Updated 5 years ago
- Contains the code examples from The UVM Primer Book sorted by chapters.☆610Dec 24, 2021Updated 4 years ago
- This is the repository for the IEEE version of the book☆80Sep 29, 2020Updated 5 years ago