marcoz001 / axi-uvm
yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
☆111Updated 7 years ago
Alternatives and similar repositories for axi-uvm:
Users that are interested in axi-uvm are comparing it to the libraries listed below
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆147Updated 4 years ago
- UVM AHB VIP☆81Updated 3 months ago
- VIP for AXI Protocol☆122Updated 2 years ago
- UVM examples and projects☆126Updated 6 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆166Updated 6 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆138Updated 6 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆85Updated last year
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆101Updated 2 months ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆119Updated 3 years ago
- Verification IP for I2C protocol☆41Updated 3 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆31Updated 4 years ago
- This is the main repository for all the examples for the book Practical UVM☆183Updated 4 years ago
- uvm AXI BFM(bus functional model)☆240Updated 11 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆58Updated last year
- SystemVerilog VIP for AMBA APB protocol☆71Updated 3 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆93Updated 7 years ago
- UVM Generator☆44Updated 10 months ago
- Novel GUI Based UVM Testbench Template Builder☆125Updated 3 years ago
- a very simple risc_cpu verification demo with uvm☆22Updated 5 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆48Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆48Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆100Updated 11 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆53Updated 8 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆42Updated 4 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- Verification IP for APB protocol☆59Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- Reference examples and short projects using UVM Methodology☆260Updated 2 years ago