designsolver / ahb2apb_bridge_vip
AHB to APB Bridge VIP
☆29Updated 6 years ago
Alternatives and similar repositories for ahb2apb_bridge_vip:
Users that are interested in ahb2apb_bridge_vip are comparing it to the libraries listed below
- Verification IP for APB protocol☆62Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆50Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- a very simple risc_cpu verification demo with uvm☆22Updated 5 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆44Updated 4 years ago
- ☆40Updated last year
- UART design in SV and verification using UVM and SV☆43Updated 5 years ago
- Verification IP for I2C protocol☆41Updated 3 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆10Updated 4 months ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆38Updated 4 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆31Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 2 years ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆31Updated 4 years ago
- ☆21Updated 3 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆31Updated 2 years ago
- UVM AHB VIP☆83Updated 5 months ago
- UVM Verification IP to uart2bus IP.☆22Updated 3 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- Maven Silicon Project☆17Updated 6 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆113Updated 7 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆49Updated 4 years ago
- generate UVM testbench using python☆27Updated 7 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- ☆25Updated 3 years ago
- Verification AXI-4 bus standard using UVM and System Verilog☆15Updated 7 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- Development of AXI4 Accelerated VIP☆28Updated 2 years ago
- This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).☆13Updated 3 years ago
- Verification IP for APB protocol☆26Updated 4 years ago