Alternatives and similar repositories for UIUC-IMC-Benchmarking

Users that are interested in UIUC-IMC-Benchmarking are comparing it to the libraries listed below

• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆53Updated last year
• vaughnbetz / COFFE
  ☆46Updated last year
• neurosim / 3D_NeuroSim_V1.0
  Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration
  ☆25Updated 4 years ago
• UT-LCA / ML4Accel-Dataset
  Dataset for ML-guided Accelerator Design
  ☆43Updated last year
• akdimitri / RRAM_COMPILER
  This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…
  ☆77Updated 3 years ago
• spcl / rapidchiplet
  A toolchain for rapid design space exploration of chiplet architectures
  ☆72Updated 6 months ago
• VeriGOOD-ML / public
  ☆65Updated 9 months ago
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆92Updated last year
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• The-OpenROAD-Project / DAC-2020-Tutorial
  Material for OpenROAD Tutorial at DAC 2020
  ☆46Updated 3 years ago
• neurosim / DNN_NeuroSim_V1.2
  Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)
  ☆10Updated 4 years ago
• ehw-fit / evoapproxlib
  Library of approximate arithmetic circuits
  ☆61Updated 2 weeks ago
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆104Updated 2 weeks ago
• sharc-lab / HLSFactory
  HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond
  ☆48Updated 2 weeks ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆83Updated 4 years ago
• zlinaf / PowerGear
  [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs
  ☆20Updated 3 years ago
• magical-eda / OpenSAR
  ☆16Updated 4 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆91Updated 10 months ago
• pnnl / soda-opt
  ☆56Updated 6 months ago
• diwu1990 / uSystolic-Sim
  A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
  ☆84Updated 4 years ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆152Updated last week
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆56Updated last year
• The-OpenROAD-Project / asap5
  ☆38Updated 2 years ago
• UCLA-VAST / FlexCNN
  ☆72Updated 2 years ago
• sharc-lab / LightningSim
  A fast, accurate trace-based simulator for High-Level Synthesis.
  ☆74Updated last month
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆55Updated last year
• cornell-ece5745 / ece5745-tut8-sram
  ECE 5745 Tutorial 8: SRAM Generators
  ☆15Updated 3 years ago
• baichen318 / boom-explorer-public
  The open-sourced version of BOOM-Explorer
  ☆45Updated 2 years ago
• bsc-loca / sauria
  SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…
  ☆79Updated 2 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆79Updated last month