UIUC-IMC / UIUC-IMC-Benchmarking
☆15Updated this week
Related projects ⓘ
Alternatives and complementary repositories for UIUC-IMC-Benchmarking
- Dataset for ML-guided Accelerator Design☆31Updated this week
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆65Updated 3 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆21Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆46Updated 3 years ago
- Library of approximate arithmetic circuits☆51Updated 2 years ago
- ☆38Updated 2 months ago
- An Open-Source Tool for CGRA Accelerators☆57Updated 3 months ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆55Updated 2 years ago
- ☆70Updated last year
- A list of our chiplet simulaters☆21Updated 3 years ago
- RTL implementation of Flex-DPE.☆91Updated 4 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆13Updated 2 years ago
- ☆51Updated 10 months ago
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆30Updated this week
- An integrated CGRA design framework☆83Updated last week
- A RISC-V BOOM Microarchitecture Power Modeling Framework☆19Updated last year
- ☆29Updated last year
- ☆37Updated 4 months ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- QuickEst repository: Quick Estimation of Quality of Results☆26Updated 6 years ago
- This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top…☆41Updated last year
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆31Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆59Updated 3 years ago
- The open-sourced version of BOOM-Explorer☆32Updated last year
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆71Updated 3 months ago
- An Open-Source Tool for CGRA Accelerators☆17Updated 7 months ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆47Updated 2 weeks ago
- A toolchain for rapid design space exploration of chiplet architectures☆33Updated 6 months ago