openpower-cores / a2oLinks
☆140Updated 3 years ago
Alternatives and similar repositories for a2o
Users that are interested in a2o are comparing it to the libraries listed below
Sorting:
- ☆247Updated 2 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆203Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆174Updated 3 weeks ago
- ☆61Updated 4 years ago
- OmniXtend cache coherence protocol☆82Updated 4 years ago
- ☆238Updated 2 years ago
- RISC-V Processor Trace Specification☆182Updated 2 weeks ago
- Riscy Processors - Open-Sourced RISC-V Processors☆74Updated 6 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆108Updated 2 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆229Updated 6 months ago
- Tile based architecture designed for computing efficiency, scalability and generality☆257Updated 2 weeks ago
- Working draft of the proposed RISC-V Bitmanipulation extension☆211Updated last year
- ☆86Updated 3 years ago
- FPGA reference design for the the Swerv EH1 Core☆71Updated 5 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆156Updated 4 years ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆141Updated this week
- RISC-V Torture Test☆195Updated 10 months ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆47Updated 2 weeks ago
- RISC-V CPU Core☆327Updated 11 months ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆85Updated 4 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆224Updated last year
- VeeR EL2 Core☆278Updated last week
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆57Updated 5 years ago
- ☆175Updated last year
- ☆46Updated 3 weeks ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆152Updated 3 years ago
- ☆287Updated 2 months ago
- ☆84Updated 3 weeks ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆98Updated 3 years ago
- ☆150Updated last year