openpower-cores / a2oLinks
☆142Updated 3 years ago
Alternatives and similar repositories for a2o
Users that are interested in a2o are comparing it to the libraries listed below
Sorting:
- ☆247Updated 3 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 5 years ago
- A tiny POWER Open ISA soft processor written in Chisel☆112Updated 2 years ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆51Updated 6 months ago
- OmniXtend cache coherence protocol☆82Updated 6 months ago
- ☆61Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆180Updated 7 months ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated last year
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆151Updated 3 weeks ago
- RISC-V Processor Trace Specification☆198Updated 2 months ago
- OpenSPARC-based SoC☆73Updated 11 years ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated 2 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 6 years ago
- ☆51Updated 2 months ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- An open standard Cache Coherent Fabric Interface repository☆66Updated 6 years ago
- ☆113Updated 4 years ago
- ☆250Updated 2 years ago
- RiscyOO: RISC-V Out-of-Order Processor☆165Updated 5 years ago
- OpenRISC 1200 implementation☆174Updated 10 years ago
- ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 archite…☆78Updated 3 years ago
- 64-bit multicore Linux-capable RISC-V processor☆101Updated 7 months ago
- The OpenRISC 1000 architectural simulator☆75Updated 7 months ago
- ☆87Updated 2 weeks ago
- ☆89Updated 3 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆151Updated last year
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆242Updated 6 months ago
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆247Updated last year
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Updated 6 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago