openpower-cores / a2oLinks
☆140Updated 3 years ago
Alternatives and similar repositories for a2o
Users that are interested in a2o are comparing it to the libraries listed below
Sorting:
- ☆247Updated 3 years ago
- OmniXtend cache coherence protocol☆82Updated 5 months ago
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆51Updated 6 months ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆202Updated 4 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆177Updated 6 months ago
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆149Updated last week
- OpenSPARC-based SoC☆72Updated 11 years ago
- ☆61Updated 4 years ago
- FPGA reference design for the the Swerv EH1 Core☆72Updated 5 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆235Updated 11 months ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- A tiny POWER Open ISA soft processor written in Chisel☆111Updated 2 years ago
- ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform☆50Updated 3 years ago
- ☆50Updated last month
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆86Updated 4 years ago
- RISC-V Processor Trace Specification☆196Updated last month
- The OpenRISC 1000 architectural simulator☆74Updated 6 months ago
- ☆247Updated 2 years ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- ☆113Updated 4 years ago
- 64-bit multicore Linux-capable RISC-V processor☆99Updated 6 months ago
- RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions☆76Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆164Updated 5 years ago
- ☆300Updated last week
- Advanced Interface Bus (AIB) die-to-die hardware open source☆142Updated last year
- 4 stage, in-order, compute RISC-V core based on the CV32E40P☆246Updated last year
- OpenRISC 1200 implementation☆173Updated 10 years ago
- Experiments with fixed function renderers and Chisel HDL☆59Updated 6 years ago
- Workshop on Computer Architecture Research with RISC-V (CARRV)☆41Updated last year
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆102Updated 4 years ago