OpenPOWERFoundation / a2iLinks
The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
☆48Updated 3 years ago
Alternatives and similar repositories for a2i
Users that are interested in a2i are comparing it to the libraries listed below
Sorting:
- The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …☆52Updated 8 months ago
- J-Core J2/J32 5 stage pipeline CPU core☆61Updated 5 years ago
- MR1 formally verified RISC-V CPU☆56Updated 7 years ago
- OpenSPARC-based SoC☆75Updated 11 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 8 months ago
- OpenGL 1.x implementation for FPGAs☆111Updated this week
- Exploring gate level simulation☆58Updated 9 months ago
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆223Updated last year
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …☆29Updated 2 months ago
- IRSIM switch-level simulator for digital circuits☆35Updated 2 months ago
- Design digital circuits in C. Simulate really fast with a regular compiler.☆177Updated 2 weeks ago
- A tiny POWER Open ISA soft processor written in Chisel☆113Updated 2 years ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆77Updated this week
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- SoftCPU/SoC engine-V☆55Updated 10 months ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆58Updated 2 years ago
- 😎 A curated list of awesome RISC-V implementations☆142Updated 2 years ago
- ☆33Updated 5 years ago
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- CoreScore☆171Updated 2 months ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated 3 weeks ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆39Updated 3 weeks ago
- A RISC-V CPU implementation☆16Updated 5 years ago
- Optimized RISC-V FP emulation for 32-bit processors☆36Updated 4 years ago
- A pipelined RISC-V processor☆63Updated 2 years ago
- Graphics demos☆111Updated last year
- 64-bit multicore Linux-capable RISC-V processor☆105Updated 9 months ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆67Updated 9 months ago
- ☆144Updated 3 years ago