Alternatives and similar repositories for pyhdlsim

Users that are interested in pyhdlsim are comparing it to the libraries listed below

• vlotnik / uvm_sin_cos_table
  Contains source code for sin/cos table verification using UVM
  ☆20Updated 4 years ago
• FPGA-Systems / drawio-hdl-builder
  Drawio => VHDL and Verilog
  ☆57Updated last year
• AsFigo / pyslint
  SystemVerilog Linter based on pyslang
  ☆31Updated 3 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆73Updated last week
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆54Updated last year
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆78Updated 3 years ago
• mohamed / fsm2sv
  SystemVerilog FSM generator
  ☆32Updated last year
• fvutils / pyhdl-if
  Python interface for cross-calling with HDL
  ☆35Updated 2 weeks ago
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 4 years ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆71Updated 3 weeks ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆53Updated last year
• themperek / spicebind
  SpiceBind – spice inside HDL simulator
  ☆53Updated last month
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆56Updated 2 months ago
• pulp-platform / svase
  ☆32Updated 7 months ago
• rggen / rggen-sv-rtl
  Common SystemVerilog RTL modules for RgGen
  ☆13Updated 2 months ago
• serge0699 / verif_elective_miet
  Репозиторий факультатива по функциональной верификации НИУ МИЭТ
  ☆13Updated last year
• tmeissner / formal_hw_verification
  Trying to verify Verilog/VHDL designs with formal methods and tools
  ☆42Updated last year
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆28Updated last year
• Nic30 / hwtLib
  hardware library for hwt (= ipcore repo)
  ☆43Updated last month
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆35Updated last week
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• snishizawa / libretto
  Characterizer
  ☆30Updated 2 weeks ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 6 months ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆54Updated 5 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆59Updated 2 years ago
• Nic30 / hdlConvertorAst
  Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
  ☆38Updated 2 months ago
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆25Updated 5 months ago
• Kuree / pysv
  Running Python code in SystemVerilog
  ☆70Updated 2 months ago
• oddball / ipxact2systemverilog
  Translates IPXACT XML to synthesizable VHDL or SystemVerilog
  ☆63Updated 2 weeks ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated last month