kooltzh / xilinx-coe-generatorLinks
Python script for generating Xilinx .coe files for RAM initializing
☆18Updated 6 years ago
Alternatives and similar repositories for xilinx-coe-generator
Users that are interested in xilinx-coe-generator are comparing it to the libraries listed below
Sorting:
- Wishbone interconnect utilities☆43Updated 9 months ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆82Updated last year
- Sata 2 Host Controller for FPGA implementation☆18Updated 8 years ago
- Small (Q)SPI flash memory programmer in Verilog☆65Updated 3 years ago
- Minimal DVI / HDMI Framebuffer☆82Updated 5 years ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…