Python script for generating Xilinx .coe files for RAM initializing
☆18Jan 3, 2019Updated 7 years ago
Alternatives and similar repositories for xilinx-coe-generator
Users that are interested in xilinx-coe-generator are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated last month
- A flexible, simple, yet powerful FPGA development board.☆17Feb 7, 2018Updated 8 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Dec 20, 2013Updated 12 years ago
- Cross compile FPGA tools☆21Jan 4, 2021Updated 5 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Development Kit☆33Apr 23, 2019Updated 6 years ago
- Identifies ASL Hand Gesture for numbers using image processing in verilog☆14May 3, 2012Updated 13 years ago
- core files for the MiST fpga☆33Nov 22, 2024Updated last year
- Acorn Atom in minimal configuration for iCE40 HX8K board and ICOboard☆11Apr 30, 2023Updated 2 years ago
- AXI Stream UART (verilog)☆12Oct 3, 2019Updated 6 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆83Oct 6, 2022Updated 3 years ago
- Development Kit☆22Dec 21, 2019Updated 6 years ago
- IP operations in verilog (simulation and implementation on ice40)☆64Oct 24, 2019Updated 6 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Experiments with Cologne Chip's GateMate FPGA architecture☆17Nov 16, 2023Updated 2 years ago
- A complete HDMI transmitter implementation in VHDL☆21Jun 27, 2025Updated 8 months ago
- Simplified environment for litex☆14Oct 5, 2020Updated 5 years ago
- ☆32Aug 21, 2025Updated 7 months ago
- Portable HyperRAM controller☆65Dec 8, 2024Updated last year
- ☆20Jun 18, 2022Updated 3 years ago
- Revamp / enhancements of the FPGA part of the Firebee project☆12Apr 26, 2014Updated 11 years ago
- This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codeba…☆17May 4, 2024Updated last year
- FPGA-based SDK projects for SCRx cores☆18Jan 19, 2022Updated 4 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Collection of Raspberry Pi Pico board adapters for use with Pico-DirtyJTAG☆14Jun 5, 2024Updated last year
- PCXT port for Xilinx Spartan 6 FPGAs by spark2k06☆13May 21, 2023Updated 2 years ago
- Programmable Arcade Circuit Emulation☆15Oct 14, 2017Updated 8 years ago
- Imaging application using MIPI and DisplayPort to process image☆25Feb 13, 2020Updated 6 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Nov 12, 2025Updated 4 months ago
- Gateware for USB2Sniffer☆30May 13, 2021Updated 4 years ago
- C88 is Homebrew CPU that has a ram that is only 8x8 Bits in size. It'll fit on a papilio one 500k which has enough pins for all the switc…☆18Jun 1, 2021Updated 4 years ago
- ☆14Dec 10, 2022Updated 3 years ago
- Getting started with RISC-V☆14Jun 4, 2023Updated 2 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- Interfacing VHDL and foreign languages with VUnit☆15Feb 20, 2020Updated 6 years ago
- Example projects for Quokka FPGA toolkit☆37Mar 4, 2026Updated 3 weeks ago
- A small ANSI C static library to control terminals compatible with ANSI/ISO/VT-100 control sequences.☆18May 5, 2021Updated 4 years ago
- Dot commands for esxDOS and UnoDOS3☆12Jan 21, 2022Updated 4 years ago
- Use OpenCV to convert a raw bayer image from a sensor to rgb☆12Apr 2, 2011Updated 14 years ago
- Oscilloscope for the RP2040 - OpenHantek protocol☆15Oct 28, 2025Updated 4 months ago
- Verilog I2C Slave☆24Aug 11, 2014Updated 11 years ago