Alternatives and similar repositories for riscv

Users that are interested in riscv are comparing it to the libraries listed below

• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆128Updated 5 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆141Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆137Updated 6 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆83Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 4 years ago
• jamieiles / uart
  Verilog UART
  ☆173Updated 12 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆122Updated 4 years ago
• tommythorn / yarvi
  Yet Another RISC-V Implementation
  ☆94Updated 9 months ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆107Updated last year
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 4 months ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆306Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆144Updated last month
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆115Updated last year
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆125Updated 2 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆81Updated 5 years ago
• Lampro-Mellon / LM-RISCV-DV
  An Open-Source Design and Verification Environment for RISC-V
  ☆83Updated 4 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆260Updated 2 months ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆99Updated last year
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆271Updated 4 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆167Updated this week
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆111Updated this week
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆149Updated last year
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆181Updated 3 weeks ago
• IObundle / iob-soc
  RISC-V System on Chip Template
  ☆158Updated 3 weeks ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆93Updated last week
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆192Updated 3 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆87Updated 4 months ago