Alternatives and similar repositories for risc63:

Users that are interested in risc63 are comparing it to the libraries listed below

• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆28Updated 3 weeks ago
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆49Updated last week
• tommythorn / tinytapeout-4-bit-cpu
  A design for TinyTapeout
  ☆15Updated 2 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆81Updated last year
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆37Updated last year
• chipsalliance / yosys-f4pga-plugins
  Plugins for Yosys developed as part of the F4PGA project.
  ☆80Updated 8 months ago
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆79Updated 4 years ago
• PacoReinaCampo / PU-RISCV
  Processing Unit with RISCV-32 / RISCV-64 / RISCV-128
  ☆19Updated 3 weeks ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆38Updated last month
• stnolting / neorv32-riscof
  ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆30Updated this week
• efabless / caravel_board
  ☆32Updated 2 months ago
• pepijndevos / seqpu
  A bit-serial CPU
  ☆18Updated 5 years ago
• leos313 / DOOM_FPGA
  Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs
  ☆16Updated 4 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆27Updated last month
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• thinkoco / de10-nano-riscv
  A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano
  ☆34Updated 4 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆40Updated 2 years ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆48Updated this week
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆24Updated 4 years ago
• efabless / mpw_precheck
  ☆36Updated 3 months ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆37Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆39Updated last year
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 7 months ago
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated 2 years ago
• hgeisse / eco32
  32-Bit RISC microprocessor system for FPGA boards
  ☆37Updated last month
• olofk / simple_spi
  SPI core
  ☆15Updated 5 years ago
• jbush001 / MiteCPU
  Minimal microprocessor
  ☆20Updated 7 years ago
• Dmitriy0111 / nanoFOX
  A small RISC-V core (SystemVerilog)
  ☆31Updated 5 years ago