Alternatives and similar repositories for risc63:

Users that are interested in risc63 are comparing it to the libraries listed below

• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆32Updated last week
• epsilon537 / boxlambda
  FPGA based microcomputer sandbox for software and RTL experimentation
  ☆54Updated this week
• taneroksuz / fpu-sp
  IEEE 754 single precision floating point library in systemverilog and vhdl
  ☆29Updated 4 months ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆51Updated 3 years ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆32Updated last week
• pulp-platform / pulp-ethernet
  ☆13Updated 3 weeks ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆61Updated 11 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆41Updated 4 months ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆46Updated 11 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆42Updated 2 months ago
• jbush001 / ChiselGPU
  Experiments with fixed function renderers and Chisel HDL
  ☆59Updated 6 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• shalan / Awesome-Sky130-IPs
  ☆10Updated last year
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated last month
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆44Updated 2 years ago
• openrisc / or1k_marocchino
  OpenRISC processor IP core based on Tomasulo algorithm
  ☆32Updated 3 years ago
• ZipCPU / dbgbus
  A collection of debugging busses developed and presented at zipcpu.com
  ☆41Updated last year
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆79Updated last month
• openhwgroup / cv32e41p
  4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions
  ☆27Updated last year
• mattvenn / magic-inverter
  an inverter drawn in magic with makefile to simulate
  ☆26Updated 2 years ago
• ultraembedded / core_uriscv
  Another tiny RISC-V implementation
  ☆54Updated 3 years ago
• efabless / caravel_board
  ☆34Updated 5 months ago
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆19Updated last month
• ChrisPVille / jtaglet
  Easy-to-use JTAG TAP and Debug Controller core written in Verilog
  ☆28Updated 6 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆40Updated 11 months ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆45Updated last year
• verilator / verilator_ext_tests
  Extended and external tests for Verilator testing
  ☆16Updated last week
• aniketnk / circular-queue-verilog
  Implementation of a circular queue in hardware using verilog.
  ☆16Updated 6 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆89Updated this week
• microsoft / Elastic-Silicon-Interconnect
  ESI is an FPGA connectivity system. It uses typed, latency-insensitive on-chip connections between ESI-enabled modules. It also bridges o…
  ☆34Updated 4 years ago