Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring
☆16Apr 22, 2026Updated last week
Alternatives and similar repositories for AuroraFlow
Users that are interested in AuroraFlow are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆12Dec 10, 2024Updated last year
- SYCL-based Stencil Simulation Framework Targeting FPGAs☆17Aug 31, 2024Updated last year
- This repository contains IPs, Vitis kernels and software APIs that can be leveraged by Vitis users to build scale-out solutions on multip…☆25Apr 27, 2023Updated 3 years ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆103Jun 30, 2025Updated 9 months ago
- A OpenCL-based FPGA benchmark suite for HPC☆37Jan 29, 2026Updated 3 months ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- The codebase that computed the Ninth Dedekind Number☆14Jan 18, 2026Updated 3 months ago
- Open source Photonics PDK for VTT's 3 um SOI platform.☆14Apr 15, 2026Updated 2 weeks ago
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆13Jul 16, 2024Updated last year
- This is a personal archive. Please refer to github.com/UCLA-VAST/RapidStream☆15May 31, 2022Updated 3 years ago
- understanding of cocotb (In Chinese Only)☆22Jun 10, 2025Updated 10 months ago
- Alveo Versal Example Design☆65Jan 28, 2026Updated 3 months ago
- (Not actively updating)Vision Transformer Accelerator implemented in Vivado HLS for Xilinx FPGAs.☆20Dec 29, 2024Updated last year
- ☆18Nov 6, 2024Updated last year
- A research shell for Alveo V80☆32Apr 22, 2026Updated last week
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆22Nov 21, 2020Updated 5 years ago
- A branch predictor simulator in C++ that tests 6 different types of branch predictors.☆13Apr 26, 2018Updated 8 years ago
- ☆12Nov 27, 2021Updated 4 years ago
- ☆12Jun 12, 2023Updated 2 years ago
- Sources and instructions for building an Intel(r) Edison-based monitoring system witih motion detection and cloud/social connection☆20Aug 20, 2017Updated 8 years ago
- Record MPI operations on tape☆25Dec 13, 2023Updated 2 years ago
- Scaling Graph Processing on HBM-enabled FPGAs with Heterogeneous Pipelines☆22Aug 8, 2022Updated 3 years ago
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- Gaia DR3 has 6.6M quasar candidates! We construct a new quasar catalog for cosmology with them.☆10Feb 11, 2026Updated 2 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A terminal text editor written in MoonBit☆11Apr 7, 2025Updated last year
- The Task Parallel System Composer (TaPaSCo)☆125Apr 22, 2026Updated last week
- SimuLTE with CV2X Mode 4 integration☆23May 8, 2024Updated last year
- ☆14May 15, 2023Updated 2 years ago
- FITS to Azimuth/Elevation using Astrometry.net--calibrate and plate scale images☆12Feb 6, 2024Updated 2 years ago
- ☆11Mar 20, 2025Updated last year
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated 3 weeks ago
- Research paper list for host networking: in a system view☆10Jan 2, 2025Updated last year
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆25Nov 29, 2024Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- p4 controller in Rust☆12Feb 22, 2021Updated 5 years ago
- A new Hardware Design Language that keeps you in the driver's seat☆125Updated this week
- ☆11Jan 2, 2026Updated 3 months ago
- Experiments in the efficient transpose of bit-matrices.☆16Aug 31, 2015Updated 10 years ago
- Course project of UCSD CSE-240A Computer Architecture☆19Jul 8, 2017Updated 8 years ago
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆19Sep 26, 2024Updated last year
- The client (calculator) software of this project.☆11Mar 25, 2023Updated 3 years ago