microsoft / PanopticonLinks
Panopticon is a complete in-DRAM RowHammer mitigation. This code simulates an implementation of Panopticon in DDR5.
☆14Updated 2 years ago
Alternatives and similar repositories for Panopticon
Users that are interested in Panopticon are comparing it to the libraries listed below
Sorting:
- Code for experiments referenced in the Usenix Security 2017 paper "Strong and Efficient Cache Side-Channel Protection using Hardware Tran…☆15Updated 3 years ago
- Criticality-aware Framework for Modeling Computer Performance☆33Updated last year
- A heterogeneous architecture timing model simulator.☆174Updated 4 months ago
- Shielded Enclaves for Cloud FPGAs☆15Updated 4 years ago
- HW interface for memory caches☆28Updated 5 years ago
- GPUReplay, ASPLOS 2022☆41Updated 3 years ago
- ☆14Updated 4 years ago
- Using Data Memory-Dependent Prefetchers to Leak Data at Rest☆38Updated 3 years ago
- ☆16Updated 3 years ago
- PIN-based Fault-Injector is a fault injector based on the Intel PIN tool. For more information, please refer to the following paper:☆18Updated 7 years ago
- RISC-V Security Model☆34Updated last month
- ☆48Updated 7 years ago
- A library for PCIe Transaction Layer☆61Updated 3 years ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆28Updated 7 months ago
- Opening Pandora's Box: A Systematic Study of New Ways Microarchitecture can Leak Private Data☆20Updated 3 years ago
- ☆16Updated 10 months ago
- Memory consistency model checking and test generation library.☆16Updated 9 years ago
- CleanupSpec (MICRO-2019)☆16Updated 5 years ago
- ☆36Updated 6 years ago
- Pathfinder: High-Resolution Control-Flow Attacks Exploiting the Conditional Branch Predictor☆21Updated last year
- This repository contains some tools to monitor the UNC_CBO_CACHE_LOOKUP event of the C-Boxes.☆12Updated 8 years ago
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆13Updated 5 years ago
- Sampled simulation of multi-threaded applications using LoopPoint methodology☆24Updated 5 months ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Updated 5 years ago
- An LLVM pass to profile dynamic LLVM IR instructions and runtime values☆141Updated 5 years ago
- Proof-of-concept code for the IEEE S&P 2025 paper "Peek-a-Walk: Leaking Secrets via Page Walk Side Channels"☆31Updated 6 months ago
- ☆76Updated 9 months ago
- ☆17Updated 3 years ago
- MIRAGE (USENIX Security 2021)☆14Updated 2 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆143Updated 2 years ago