aliyun / alibabacloud-fpga

Related projects: ⓘ

• FPGA-Research-Manchester / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆24Updated 3 years ago
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆14Updated last month
• parimalp / Advanced-Embedded-System-Design-Flow-on-Zynq
  ☆17Updated 6 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆19Updated this week
• RPG-7 / HGA101_GPU
  ☆16Updated 3 years ago
• franzflasch / leiwand_rv32
  RISC-V RV32I CPU written in verilog
  ☆10Updated 4 years ago
• FPGA-Networking / HyperParser
  ☆25Updated 2 years ago
• FDU-ME-ARC / NVMeCHA
  ☆12Updated 3 years ago
• andrewattwood / fuserisc
  Dual RISC-V DISC with integrated eFPGA
  ☆15Updated 2 years ago
• FPGA-Research-Manchester / zynq-ultrascale-readback-capture
  This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…
  ☆13Updated 4 years ago
• Lombiq / Hastlayer-Hardware-Framework---Catapult
  Hardware-side component of Hastlayer for Microsoft Project Catapult FPGAs. See https://hastlayer.com for details.
  ☆11Updated 4 years ago
• PacoReinaCampo / MPSoC-NoC
  Network on Chip for MPSoC
  ☆24Updated this week
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆31Updated 10 years ago
• corundum / verilog-ethernet
  Verilog Ethernet components for FPGA implementation
  ☆14Updated last year
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated 10 months ago
• bharathk005 / Verilog_projects
  HDMI + GPU-pipeline + FFT
  ☆13Updated 8 years ago
• RoaLogic / adv_dbg_if
  Universal Advanced JTAG Debug Interface
  ☆17Updated 4 months ago
• antmicro / openssd-nvme
  ☆13Updated 3 years ago
• freecores / theia_gpu
  Theia: ray graphic processing unit
  ☆19Updated 10 years ago
• ucb-bar / hwacha-template
  Template for projects using the Hwacha data-parallel accelerator
  ☆34Updated 3 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆33Updated 3 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆28Updated 6 months ago
• furkanturan / lowrisc-zed
  LowRISC port to Zedboard
  ☆12Updated 7 years ago
• zhouzaixin / arm_soc
  ☆13Updated 5 years ago
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆32Updated 7 months ago
• SLink-Protocol / S-Link
  An Open Source Link Protocol and Controller
  ☆22Updated 3 years ago
• hdl-util / mipi-ccs
  Control a MIPI Camera over I2C
  ☆21Updated 4 years ago
• pbridd / lzrw1-compression-core
  This is the repository for a verilog implementation of a lzrw1 compression core
  ☆17Updated 6 years ago
• IBM / rocc-software
  C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
  ☆52Updated 4 years ago
• trondd / oc-i2c
  I2C controller core from Opencores.org
  ☆22Updated 12 years ago