hpb-project / BOELinks
Blockchain Offload Engine
☆15Updated 7 years ago
Alternatives and similar repositories for BOE
Users that are interested in BOE are comparing it to the libraries listed below
Sorting:
- TCP Offload Engine☆77Updated 8 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Updated last year
- Groundhog - Serial ATA Host Bus Adapter☆24Updated 7 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆31Updated 7 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 5 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Updated 6 years ago
- LIS Network-on-Chip Implementation☆34Updated 9 years ago
- ☆36Updated 2 years ago
- ☆35Updated 3 years ago
- verification of simple axi-based cache☆18Updated 6 years ago
- Virtio implementation in SystemVerilog☆48Updated 8 years ago
- Computational Storage Device based on the open source project OpenSSD.☆29Updated 5 years ago
- ☆16Updated 6 years ago
- ☆20Updated 4 years ago
- Wishbone SATA Controller☆24Updated 3 months ago
- Verilog PCI express components☆25Updated 2 years ago
- ☆36Updated 5 years ago
- A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark☆50Updated 4 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆22Updated 3 years ago
- DDR4 Simulation Project in System Verilog☆44Updated 11 years ago
- ☆14Updated 11 months ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- hdmi-ts Project☆13Updated 8 years ago
- UVM testbench for verifying the Pulpino SoC☆14Updated 5 years ago
- Direct Access Memory for MPSoC☆13Updated last week
- Theia: ray graphic processing unit☆20Updated 11 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆33Updated 2 years ago
- AXI X-Bar☆19Updated 5 years ago
- ☆27Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆11Updated 4 years ago