hpb-project / BOE
Blockchain Offload Engine
☆15Updated 6 years ago
Alternatives and similar repositories for BOE:
Users that are interested in BOE are comparing it to the libraries listed below
- TCP Offload Engine☆72Updated 7 years ago
- Groundhog - Serial ATA Host Bus Adapter☆21Updated 6 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆61Updated 8 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆35Updated last year
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆33Updated last year
- ☆27Updated 4 years ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- Implementation of the PCIe physical layer☆33Updated last month
- LIS Network-on-Chip Implementation☆29Updated 8 years ago
- Gigabit MAC + UDP/TCP/IP offload Engine☆31Updated 5 years ago
- corundum work on vu13p☆18Updated last year
- 1000BASE-X IEEE 802.3-2008 Clause 36 - Physical Coding Sublayer (PCS)☆18Updated 10 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆30Updated 6 years ago
- ☆28Updated 7 years ago
- PCIe DMA Subsystem based on Xilinx XAPP1171☆46Updated last year
- Extensible FPGA control platform☆57Updated last year
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆43Updated 4 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- Open source FPGA-based NIC and platform for in-network compute☆60Updated 3 months ago
- ☆53Updated 2 years ago
- WISHBONE Interconnect☆11Updated 7 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆68Updated 8 months ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆33Updated 4 years ago
- Cryptonight Monero Verilog code for ASIC☆20Updated 6 years ago
- DDR3 SDRAM controller☆18Updated 10 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- Simple hash table on Verilog (SystemVerilog)☆48Updated 8 years ago
- ☆29Updated 2 years ago
- Open FPGA Modules☆23Updated 4 months ago