hpb-project / BOELinks
Blockchain Offload Engine
☆15Updated 7 years ago
Alternatives and similar repositories for BOE
Users that are interested in BOE are comparing it to the libraries listed below
Sorting:
- TCP Offload Engine☆72Updated 7 years ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆14Updated 6 years ago
- Open source FPGA-based NIC and platform for in-network compute☆66Updated 8 months ago
- Wishbone SATA Controller☆19Updated last month
- Groundhog - Serial ATA Host Bus Adapter☆22Updated 7 years ago
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆38Updated last year
- ☆30Updated last year
- Open-Channel Open-Way Flash Controller☆17Updated 3 years ago
- A versatile Wireshark-compatible packet filter, capable of 100G speeds and higher. Also known as FFShark☆49Updated 4 years ago
- ☆33Updated 4 years ago
- NVMe Controller featuring Hardware Acceleration☆90Updated 4 years ago
- hdmi-ts Project☆13Updated 8 years ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆65Updated 8 years ago
- LIS Network-on-Chip Implementation☆30Updated 8 years ago
- SHA-256 IP core for ZedBoard (Zynq SoC)☆30Updated 7 years ago
- A lightweight Ethernet MAC Controller IP for FPGA prototyping☆14Updated 4 years ago
- Verilog Ethernet Switch (layer 2)☆45Updated last year
- Generic AXI master stub☆19Updated 11 years ago
- Computational Storage Device based on the open source project OpenSSD.☆26Updated 4 years ago
- Simple hash table on Verilog (SystemVerilog)☆49Updated 9 years ago
- ☆35Updated 3 years ago
- LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G☆39Updated 2 years ago
- ☆69Updated 3 years ago
- Works in Progress and Experiments for the Innova-2 Flex XCKU15P-based Board☆14Updated last year
- Implementation of the PCIe physical layer☆45Updated last week
- ☆18Updated 3 years ago
- An open-source RTL NVMe controller IP for Xilinx FPGA.☆53Updated 4 years ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆18Updated 5 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago