Blockchain Offload Engine
☆17May 5, 2018Updated 8 years ago
Alternatives and similar repositories for BOE
Users that are interested in BOE are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TCP Offload Engine☆79Nov 18, 2017Updated 8 years ago
- ☆14Dec 14, 2021Updated 4 years ago
- go-hpb main chain master☆55Oct 25, 2023Updated 2 years ago
- ☆15Aug 1, 2023Updated 3 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Apr 6, 2023Updated 3 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- HPB ico contracts☆67Aug 25, 2017Updated 9 years ago
- Gowin USB3.0 Device Controller IP☆18Aug 20, 2024Updated 2 years ago
- Xilinx IP repository☆13May 5, 2018Updated 8 years ago
- corundum work on vu13p☆23Nov 10, 2023Updated 2 years ago
- IP Catalog for Raptor.☆18Dec 6, 2024Updated last year
- eXchangily DEX mobile App☆20Nov 1, 2023Updated 2 years ago
- Banyan Network open source project of Multi-Trust Connector.☆11Dec 13, 2018Updated 7 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆19Feb 20, 2019Updated 7 years ago
- Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.☆16Jan 3, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…☆16Jun 29, 2019Updated 7 years ago
- ☆39Mar 10, 2021Updated 5 years ago
- Tool for updating the contents of BlockRAMs found in Xilinx 7 series bitstreams.☆19Feb 9, 2022Updated 4 years ago
- Radio Spectrum Viewer and Software Defined Radio in a cheap FPGA board☆21Apr 24, 2023Updated 3 years ago
- ☆174Sep 30, 2026Updated 2 weeks ago
- [ARCHIVED] PancakeSwap v2 subgraph☆18Apr 8, 2021Updated 5 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆16Nov 8, 2025Updated 11 months ago
- ☆43Jul 4, 2026Updated 3 months ago
- AXI4-Compatible Verilog Cores, along with some helper modules.☆17Mar 14, 2020Updated 6 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- MATLAB toolbox for ADI high speed converter products☆26Sep 8, 2026Updated last month
- Fast Access Blockchain☆30Apr 18, 2024Updated 2 years ago
- A go implementation of rfc's 6762 and 6763☆12Feb 6, 2023Updated 3 years ago
- Various examples of how to use the Humble Toolkit.☆13Aug 31, 2016Updated 10 years ago
- A 32 point radix-2 FFT module written in Verilog☆25Jun 28, 2020Updated 6 years ago
- Chisel NVMe controller☆29Nov 24, 2022Updated 3 years ago
- Hdac Document☆23Jul 25, 2018Updated 8 years ago
- A module for TBT3☆48May 11, 2026Updated 5 months ago
- NVMe Controller featuring Hardware Acceleration☆122Jun 23, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ☆22Jul 28, 2021Updated 5 years ago
- A Python 3 C++ extension to simplify development using USRP software-defined radios.☆12Mar 16, 2026Updated 7 months ago
- LimeSDR ExtIO Plugin for HDSDR☆16Jul 29, 2020Updated 6 years ago
- Extension to operate Matlab in VS Code☆10Sep 15, 2022Updated 4 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆32Oct 30, 2015Updated 10 years ago
- SOC system using verilog on FPGA devices.☆10Jan 11, 2016Updated 10 years ago
- ☆30Apr 1, 2017Updated 9 years ago