Alternatives and similar repositories for XilinxVirtualCable

Users that are interested in XilinxVirtualCable are comparing it to the libraries listed below

• enjoy-digital / usb3_pipe
  USB3 PIPE interface for Xilinx 7-Series
  ☆217Updated 3 years ago
• derekmulcahy / xvcpi
  Xilinx Virtual Cable Server for Raspberry Pi
  ☆115Updated 3 years ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆232Updated 2 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆256Updated 5 months ago
• tmbinc / xvcd
  Xilinx Virtual Cable Daemon
  ☆118Updated 4 months ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆298Updated 2 months ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆277Updated 2 weeks ago
• CospanDesign / nysa-sata
  ☆85Updated 8 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆623Updated 4 months ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆124Updated 2 years ago
• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆203Updated last year
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆359Updated 3 weeks ago
• hamsternz / DisplayPort_Verilog
  A Verilog implementation of DisplayPort protocol for FPGAs
  ☆250Updated 6 years ago
• ultraembedded / core_ft60x_axi
  FTDI FT600 SuperSpeed USB3.0 to AXI bus master
  ☆94Updated 5 years ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆487Updated 3 years ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆134Updated 2 years ago
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆391Updated last week
• damdoy / ice40_ultraplus_examples
  Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
  ☆273Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆143Updated 2 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆72Updated last year
• jamieiles / uart
  Verilog UART
  ☆172Updated 12 years ago
• maswx / vu13p
  国产VU13P加速卡资料
  ☆73Updated 3 months ago
• litex-hub / litex-boards
  LiteX boards files
  ☆417Updated this week
• f4pga / f4pga-arch-defs
  FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
  ☆290Updated this week
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆571Updated 2 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆117Updated last month
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆80Updated 4 years ago
• yol / ethernet_mac
  Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
  ☆171Updated last year
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆150Updated 4 months ago
• enjoy-digital / litepcie
  Small footprint and configurable PCIe core
  ☆563Updated last week