jfunston / MultiCacheSimLinks
A cache simulator designed to be used with memory access traces obtained from Pin (www.pintool.org)
☆23Updated 7 years ago
Alternatives and similar repositories for MultiCacheSim
Users that are interested in MultiCacheSim are comparing it to the libraries listed below
Sorting:
- ordspecsim: The Swarm architecture simulator☆24Updated 2 years ago
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- A Multiplatform benchmark designed to provide holistic, detailed and close-to-hardware view of memory system performance with family of b…☆42Updated last month
- A fast and scalable x86-64 multicore simulator☆31Updated 4 years ago
- Simulator of a memory controller to connect DRAMSim and FlashDIMMSim into one unified memory☆17Updated last year
- (elastic) cuckoo hashing☆14Updated 5 years ago
- ☆33Updated 5 years ago
- HeteroSync is a benchmark suite for performing fine-grained synchronization on tightly coupled GPUs☆30Updated last year
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 5 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆52Updated last week
- ☆20Updated 3 years ago
- ☆20Updated 5 years ago
- A fast, accurate, and easy-to-integrate memory simulator that model memory system performance with bandwidth--latency curves.☆32Updated last month
- A Shared Memory Multithreaded Graph Benchmark Suite for Multicores☆36Updated 5 months ago
- Artifact, reproducibility, and testing utilites for gem5☆23Updated 4 years ago
- The Splash-3 benchmark suite☆44Updated 2 years ago
- PARSEC Benchmark http://parsec.cs.princeton.edu 3.0-beta-20150206 ported to Ubuntu 22.04 and with proper version control and SPLASH2 port…☆102Updated 3 weeks ago
- gem5 Tips & Tricks☆70Updated 5 years ago
- gem5 configuration for intel's skylake micro-architecture☆52Updated 3 years ago
- ☆17Updated 4 years ago
- Examples of DPU programs using the UPMEM DPU SDK☆44Updated 9 months ago
- ☆22Updated 3 weeks ago
- Multiple approaches to statistical simulation for computer architects☆15Updated 5 years ago
- ☆20Updated 4 years ago
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆76Updated 2 months ago
- Victima is a new software-transparent technique that greatly extends the address translation reach of modern processors by leveraging the…☆31Updated 2 years ago
- ☆13Updated 10 years ago
- ☆26Updated 3 weeks ago
- This is where gem5 based DRAM cache models live.☆18Updated 2 years ago
- Memory System Microbenchmarks☆64Updated 2 years ago