Alternatives and similar repositories for nmigen-zynq:

Users that are interested in nmigen-zynq are comparing it to the libraries listed below

• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆88Updated 7 months ago
• hgomersall / Ovenbird
  A tool for merging the MyHDL workflow with Vivado
  ☆20Updated 4 years ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆76Updated 2 years ago
• ydnatag / nmigen-cocotb
  cocotb extension for nMigen
  ☆16Updated 3 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆27Updated 3 months ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆29Updated 2 years ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 3 months ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆83Updated 9 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆60Updated 2 years ago
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆72Updated 3 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆57Updated this week
• umarcor / osvb
  Open Source Verification Bundle for VHDL and System Verilog
  ☆45Updated last year
• antmicro / warp-pipe
  ☆15Updated 8 months ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆42Updated 2 weeks ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆54Updated 2 months ago
• AL-255 / Project-Yatsuhashi-Chip1
  ☆39Updated 2 years ago
• yrrapt / analogue_design_example
  An example of analogue design using open source IC design tools
  ☆29Updated 3 years ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 8 months ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆64Updated last week
• olofk / observer
  ☆41Updated 5 years ago
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆32Updated this week
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆50Updated last year
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆39Updated 3 months ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆76Updated 3 years ago
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• m-kru / fsva
  FuseSoc Verification Automation
  ☆22Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 2 years ago