hamsternz / FPGA_GigabitTxLinks
Sending UDP packets out over a Gigabit PHY with an FPGA.
☆44Updated 9 years ago
Alternatives and similar repositories for FPGA_GigabitTx
Users that are interested in FPGA_GigabitTx are comparing it to the libraries listed below
Sorting:
- FPGA USB 1.1 Low-Speed Implementation☆35Updated 7 years ago
- An Open Source configuration of the Arty platform☆131Updated 2 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆125Updated 9 years ago
- A utility for Composing FPGA designs from Peripherals☆186Updated last year
- Featherweight RISC-V implementation☆53Updated 4 years ago
- Collection of open-source peripherals in Verilog☆183Updated 3 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Updated 7 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆93Updated 7 years ago
- Wishbone interconnect utilities☆44Updated last month
- ☆43Updated 5 years ago
- LatticeMico32 soft processor☆107Updated 11 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- ☆139Updated last week
- a playground for xilinx zynq fpga experiments☆49Updated 7 years ago
- VHDL library 4 FPGAs☆185Updated this week
- Small footprint and configurable Inter-Chip communication cores☆66Updated this week
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆82Updated 5 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆100Updated 6 years ago
- Verilog wishbone components☆123Updated 2 years ago
- A wishbone controlled scope for FPGA's☆85Updated 2 years ago
- Extensible FPGA control platform☆61Updated 2 years ago
- DPLL for phase-locking to 1PPS signal☆34Updated 9 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆71Updated 7 years ago
- CMod-S6 SoC☆45Updated 8 years ago
- This repository contains small example designs that can be used with the open source icestorm flow.☆155Updated 4 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆69Updated last month
- FuseSoC standard core library☆151Updated last month
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆47Updated last year
- Lattice iCE40 FPGA experiments - Work in progress☆106Updated 4 years ago
- Simple UART controller for FPGA written in VHDL☆105Updated 4 years ago