hamsternz / FPGA_GigabitTxLinks
Sending UDP packets out over a Gigabit PHY with an FPGA.
☆42Updated 9 years ago
Alternatives and similar repositories for FPGA_GigabitTx
Users that are interested in FPGA_GigabitTx are comparing it to the libraries listed below
Sorting:
- An Open Source configuration of the Arty platform☆131Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Verilog wishbone components☆117Updated last year
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 8 years ago
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Featherweight RISC-V implementation☆53Updated 3 years ago
- A single-wire bi-directional chip-to-chip interface for FPGAs☆124Updated 9 years ago
- a playground for xilinx zynq fpga experiments☆49Updated 6 years ago
- A wishbone controlled scope for FPGA's☆83Updated last year
- Generic Logic Interfacing Project☆46Updated 5 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆97Updated 5 years ago
- ☆41Updated 5 years ago
- Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL☆174Updated last year
- A utility for Composing FPGA designs from Peripherals☆183Updated 8 months ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- JESD204B core for Migen/MiSoC☆36Updated 4 years ago
- ☆135Updated 8 months ago
- Small footprint and configurable Inter-Chip communication cores☆60Updated last month
- Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces☆35Updated 9 months ago
- artix-7 PCIe dev board☆31Updated 7 years ago
- FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.☆56Updated 2 years ago
- Simple UART controller for FPGA written in VHDL☆101Updated 4 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 9 years ago
- iDEA FPGA Soft Processor☆15Updated 9 years ago
- Project X-Ray Database: XC7 Series☆70Updated 3 years ago
- DPLL for phase-locking to 1PPS signal☆32Updated 9 years ago