pbing / USBLinks
FPGA USB 1.1 Low-Speed Implementation
☆34Updated 6 years ago
Alternatives and similar repositories for USB
Users that are interested in USB are comparing it to the libraries listed below
Sorting:
- Wishbone interconnect utilities☆41Updated 3 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated last week
- Minimal DVI / HDMI Framebuffer☆81Updated 4 years ago
- Sending UDP packets out over a Gigabit PHY with an FPGA.☆42Updated 9 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆41Updated 4 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆29Updated 6 years ago
- Nitro USB FPGA core☆84Updated last year
- Collection of projects for various FPGA development boards☆44Updated last year
- Using the TinyFPGA BX USB code in user designs☆50Updated 6 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- Test of the USB3 IP Core from Daisho on a Xilinx device☆91Updated 5 years ago
- Generic Logic Interfacing Project☆46Updated 4 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 2 months ago
- Wishbone controlled I2C controllers☆49Updated 6 months ago
- Spen's Official OpenOCD Mirror☆50Updated 2 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆41Updated last year
- IceCore Ice40 HX based modular core☆46Updated 4 years ago
- Change part number or package in a Xilinx 7-series FPGA bitstream☆39Updated 5 years ago
- SDRAM controller with multiple wishbone slave ports☆29Updated 6 years ago