codeshaa / 16-bit-HDLC-using-VHDL

Related projects ⓘ

Alternatives and complementary repositories for 16-bit-HDLC-using-VHDL

• PulseRain / PulseRain_FP51_MCU
  PulseRain FP51 MCU, with peripherals
  ☆13Updated 6 years ago
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆14Updated 2 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆29Updated 3 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 2 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆22Updated 8 years ago
• ultraembedded / core_usb_sniffer
  USB capture IP
  ☆19Updated 4 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆12Updated 6 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆27Updated 3 years ago
• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆15Updated 4 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 3 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆36Updated 4 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• tirfil / VhdI2CSlave
  I2C Slave Interface (Vhdl)
  ☆20Updated 2 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆13Updated 7 years ago
• AdriaanSwan / Verilog-I2C-Slave
  Verilog I2C Slave
  ☆21Updated 10 years ago
• ADA007 / FTDI_User_Area_Writer
  FTDI EEPROM User Area Writer For Xilinx JTAG Programmer
  ☆12Updated 10 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆35Updated 3 years ago
• opalkelly-opensource / design-resources
  A collection of Opal Kelly provided design resources
  ☆15Updated last month
• uwemeyerbaese / DSP_with_FPGAs_ed3
  DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8
  ☆12Updated 2 years ago
• FarisHijazi / LZ4-Decompressor-Verilog
  Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language
  ☆13Updated 5 years ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 10 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆24Updated 4 years ago
• CospanDesign / nysa-sdio-device
  SDIO Device Verilog Core
  ☆22Updated 6 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆23Updated 4 years ago
• kholia / xvc-esp8266
  ESP8266 powered Xilinx Virtual Cable - Xilinx WiFi JTAG!
  ☆22Updated 3 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆24Updated 3 years ago
• HarmonInstruments / hififo
  Harmon Instruments FIFO to PCI Express interface
  ☆11Updated 3 years ago