High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
☆30Dec 1, 2016Updated 9 years ago
Alternatives and similar repositories for 16-bit-HDLC-using-VHDL
Users that are interested in 16-bit-HDLC-using-VHDL are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆32Jun 8, 2017Updated 8 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- HDLC Frame Detector Refer ITU-T Rec Q.921 $2☆16Jul 26, 2012Updated 13 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 4 years ago
- ☆20May 8, 2012Updated 13 years ago
- VHDL Modules☆24Mar 16, 2015Updated 11 years ago
- High-througput logic analyzer for FPGA☆16Oct 8, 2020Updated 5 years ago
- UDP/IP Core☆12Jul 17, 2014Updated 11 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆12Jul 28, 2021Updated 4 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 2 weeks ago
- include hdlc (miao), 422 grapher, 1553b☆21Oct 10, 2019Updated 6 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆17Feb 9, 2026Updated last month
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 10 years ago
- Heston implementation for Zynq with Vivado HLS☆16Jun 30, 2015Updated 10 years ago
- Yet another port of my PDP11 simulator☆22Jul 26, 2021Updated 4 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆17Jan 25, 2022Updated 4 years ago
- SDRAM controller with AXI4 interface☆103Aug 8, 2019Updated 6 years ago
- A VHDL implementation of 128 bit AES encryption with a PCIe interface.☆27Jan 9, 2017Updated 9 years ago
- VHDL package to provide C-like string formatting☆15May 6, 2022Updated 3 years ago
- Verilog I2C Slave☆24Aug 11, 2014Updated 11 years ago
- VHDL implementation of carrier phase recovery (CPR) techniques for coherent optical systems☆16Dec 6, 2020Updated 5 years ago
- Verilog IP Cores & Tests☆13May 3, 2018Updated 7 years ago
- Blackman-Harris Window functions (3-, 5-, 7-term etc.) from 1K to 64M points based only on LUTs and DSP48s FPGA resources. Main core - CO…☆13Aug 14, 2020Updated 5 years ago
- Simple Operating System for Smartcard Education☆13Mar 28, 2014Updated 11 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43May 22, 2020Updated 5 years ago
- MIPI CSI-2 RX☆38Oct 20, 2021Updated 4 years ago
- A complete Linux project for the ZYBO. This project helps me during my first steps with embedded Linux. You can find anything necessary t…☆13Oct 8, 2020Updated 5 years ago
- mirror of https://git.elphel.com/Elphel/x393_sata☆35May 12, 2020Updated 5 years ago
- ☆18Sep 16, 2020Updated 5 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- ISA-bus implementation for Arduino Mega 2560 / AVR processors☆20Sep 12, 2020Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆83Oct 6, 2022Updated 3 years ago
- Communication channel from FPGA (Alterra EP4CE10) and Linux (Lichee PI Allwinner V3S)☆29Apr 1, 2020Updated 5 years ago
- Network on Chip for MPSoC☆28Feb 28, 2026Updated 3 weeks ago
- ☆30Jul 9, 2025Updated 8 months ago
- minimal code to access ps DDR from PL☆22Oct 18, 2019Updated 6 years ago
- Verilog Implementation of Run Length Encoding for RGB Image Compression☆27Jun 28, 2021Updated 4 years ago