codeshaa / 16-bit-HDLC-using-VHDL

Related projects: ⓘ

• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆26Updated 3 years ago
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆22Updated 8 years ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆38Updated 4 years ago
• ultraembedded / core_usb_sniffer
  USB capture IP
  ☆18Updated 4 years ago
• freecores / turbo8051
  turbo 8051
  ☆28Updated 7 years ago
• hukenovs / adc_configurator
  ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)
  ☆11Updated 6 years ago
• PulseRain / PulseRain_FP51_MCU
  PulseRain FP51 MCU, with peripherals
  ☆13Updated 6 years ago
• ultraembedded / core_usb_uart
  USB serial device (CDC-ACM)
  ☆31Updated 4 years ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆24Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆21Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆28Updated 3 years ago
• defparam / PCI2Nano-RTL
  An open source FPGA PCI core & 8250-Compatible PCI UART core
  ☆38Updated 3 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 2 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 7 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆13Updated 6 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 2 years ago
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• freecores / uart16550
  UART 16550 core
  ☆29Updated 10 years ago
• ADA007 / FTDI_User_Area_Writer
  FTDI EEPROM User Area Writer For Xilinx JTAG Programmer
  ☆11Updated 10 years ago
• Bucknalla / ip_cores
  Verilog IP Cores & Tests
  ☆11Updated 6 years ago
• freecores / uart2spi
  UART To SPI
  ☆15Updated 10 years ago
• BrianHGinc / Verilog-Floating-Point-Clock-Divider
  Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…
  ☆12Updated 2 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆58Updated 5 years ago
• esynr3z / usb20dev
  USB 2.0 FS Device controller IP core written in SystemVerilog
  ☆32Updated 5 years ago
• OpenAutomationTechnologies / VHDL_IP-Cores
  ☆13Updated 4 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆39Updated 3 months ago
• jakubcabal / rmii-firewall-fpga
  RMII Firewall FPGA
  ☆18Updated 4 years ago
• jlublin / xvcd_server
  Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters
  ☆11Updated 10 years ago
• freecores / pci
  PCI bridge
  ☆14Updated 10 years ago
• HarmonInstruments / hififo
  Harmon Instruments FIFO to PCI Express interface
  ☆11Updated 3 years ago