codeshaa / 16-bit-HDLC-using-VHDLLinks
High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.
☆29Updated 8 years ago
Alternatives and similar repositories for 16-bit-HDLC-using-VHDL
Users that are interested in 16-bit-HDLC-using-VHDL are comparing it to the libraries listed below
Sorting:
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆12Updated 7 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- Verilog Repository for GIT☆33Updated 4 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Sata 2 Host Controller for FPGA implementation☆18Updated 7 years ago
- USB capture IP☆21Updated 5 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆61Updated 6 years ago
- ULPI Link Wrapper (USB Phy Interface)☆29Updated 5 years ago
- Xilinx Virtual Cable server written in python connecting Xilinx with different JTAG adapters☆11Updated 11 years ago
- ☆17Updated 4 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆29Updated 5 years ago
- Ethernet MAC 10/100 Mbps☆27Updated 3 years ago
- USB serial device (CDC-ACM)☆40Updated 5 years ago
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Provide / define the INPUT_CLK_HZ parameter and the BHG_FP_clk_divider.v will generate a clock at the specified CLK_OUT_HZ parameter usin…☆20Updated 6 months ago
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- USB Full Speed PHY☆45Updated 5 years ago
- turbo 8051☆29Updated 7 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆18Updated 2 years ago
- A general slow DDR3 interface. Very little resource consumption. Suits for all FPGAs with 1.5V IO voltage.☆38Updated last year
- Xilinx 7-series FTDI-FPGA interface through JTAG with 125 us roundtrip latency☆18Updated 6 years ago
- Small (Q)SPI flash memory programmer in Verilog☆64Updated 2 years ago
- Portable HyperRAM controller☆57Updated 8 months ago
- SPI-Flash XIP Interface (Verilog)☆43Updated 3 years ago
- Repository containing the DSP gateware cores☆13Updated last week
- Digital FM Radio Receiver for FPGA☆63Updated 9 years ago
- ☆20Updated 3 years ago
- ☆30Updated 8 years ago
- Quickly update a bitstream with new RAM contents☆15Updated 4 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆42Updated 2 years ago