accellera-official / systemc-common-practices

Related projects: ⓘ

• dcblack / sc-platform
  Example of a Virtual Platform implemented with Modern C++(14) and SystemC TLM-2.0
  ☆21Updated last year
• ben-marshall / verilog-dot
  A simple dot file / graph generator for Verilog syntax trees.
  ☆21Updated 8 years ago
• jameshanlon / netlist-paths
  A library and command-line tool for querying a Verilog netlist.
  ☆26Updated 2 years ago
• anikau31 / systemc-clang
  This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
  ☆74Updated 3 weeks ago
• accellera-official / cci
  SystemC Configuration, Control and Inspection (CCI)
  ☆12Updated 2 months ago
• accellera-official / PySysC
  Public repository for PySysC, (From SC Common Practices Subgroup)
  ☆48Updated 8 months ago
• Doulos / SystemC-Engine
  Explore the behavior SystemC kernel event-driven simulator (aka "the engine")
  ☆11Updated 8 months ago
• Minres / SystemC-Quickstart
  A simple C++ CMake project to jump-start development of SystemC models and systems
  ☆20Updated last year
• vherdt / riscv-vp
  RISC-V Virtual Prototype
  ☆35Updated 2 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆29Updated 4 months ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆44Updated this week
• StanfordVLSI / dragonphy2
  Open Source PHY v2
  ☆23Updated 4 months ago
• maltanar / systemc-chisel-tools
  A collection of tools for working with Chisel-generated hardware in SystemC
  ☆16Updated 5 years ago
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆23Updated 2 weeks ago
• SingularityKChen / SystemC-Training
  SystemC training aimed at TLM.
  ☆24Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆44Updated 7 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆28Updated last year
• Xilinx / pcie-model
  PCI Express controller model
  ☆41Updated last year
• accellera-official / crave
  Constrained RAndom Verification Enviroment (CRAVE)
  ☆14Updated 9 months ago
• chipsalliance / f4pga-sdf-timing
  Python library for working Standard Delay Format (SDF) Timing Annotation files.
  ☆28Updated 2 months ago
• pulp-platform / axi_llc
  ☆17Updated last week
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆56Updated 3 years ago
• jessebarreto / NetworkOnChip
  Development of a Network on Chip Simulation using SystemC.
  ☆30Updated 7 years ago
• IObundle / iob-lib
  Verilog Modules and Python Scripts for Creating IP Core Build Directories
  ☆29Updated 10 months ago
• hlslibs / matchlib_connections
  Matchlib Connections Library - latency insensitive channels (from NVlabs/matchlib/connections)
  ☆35Updated 2 weeks ago
• XedaHQ / xeda
  Cross EDA Abstraction and Automation
  ☆33Updated last week
• whatmough / CHIPKIT
  CHIPKIT: An agile, reusable open-source framework for rapid test chip development
  ☆38Updated 4 years ago
• IObundle / iob-mem
  Verilog behavioral description of various memories
  ☆30Updated 2 years ago