sparrowgrine / prjtritiumLinks
☆22Updated 3 years ago
Alternatives and similar repositories for prjtritium
Users that are interested in prjtritium are comparing it to the libraries listed below
Sorting:
- PicoRV☆44Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆64Updated this week
- ☆39Updated 2 years ago
- 妖刀夢渡☆59Updated 6 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Use ECP5 JTAG port to interact with user design☆28Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- ☆33Updated 2 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 4 months ago
- Generate Zynq configurations without using the vendor GUI☆30Updated last year
- Industry standard I/O for Amaranth HDL☆28Updated 7 months ago
- A configurable USB 2.0 device core☆31Updated 4 years ago
- User-friendly explanation of Yosys options☆113Updated 3 years ago
- Small footprint and configurable SPI core☆42Updated last week
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- System on Chip toolkit for Amaranth HDL☆90Updated 7 months ago
- VS Code based debugger for hardware designs in Amaranth or Verilog☆38Updated 5 months ago
- An FPGA reverse engineering and documentation project☆47Updated this week
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆97Updated 2 years ago
- Small footprint and configurable Inter-Chip communication cores☆58Updated last week
- Virtual development board for HDL design☆42Updated 2 years ago
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆29Updated 9 months ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆88Updated 6 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆51Updated last week
- Bitstream relocation and manipulation tool.☆45Updated 2 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 10 months ago
- Experimental flows using nextpnr for Xilinx devices☆47Updated this week
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆42Updated last week