Alternatives and similar repositories for ZEF:

Users that are interested in ZEF are comparing it to the libraries listed below

• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆21Updated 4 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• Xyce / Xyce_Regression
  The test suite for the Xyce Parallel Electronic Simulator
  ☆4Updated this week
• YosysHQ / sby-gui
  GUI for SymbiYosys
  ☆15Updated last year
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆50Updated 8 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆33Updated 3 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 4 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• space-tudelft / cacd
  Space CACD
  ☆12Updated 5 years ago
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆20Updated this week
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆16Updated 6 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• Qucs / qucs-help
  Qucs-Help documentation
  ☆11Updated 6 years ago
• opencomputeproject / ODSA-CDXML
  TBD
  ☆12Updated 3 months ago
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• StanfordAHA / lassen
  The PE for the second generation CGRA (garnet).
  ☆17Updated 2 weeks ago
• rbkettlewell / trollstigen-fpga
  Open source fpga project leveraging vtr CAD flow.
  ☆26Updated 2 years ago
• Vitorian / awesome-mpsoc
  Public resources available for Xilinx MPSOC+ and SDSOC hardware
  ☆18Updated 7 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• pheaver / netlist-verilog
  Netlist and Verilog Haskell Package
  ☆18Updated 14 years ago
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆33Updated last year
• devbisme / pygmyhdl
  MyHDL hardware design language encased in the tasty PygMyHDL wrapper.
  ☆19Updated 2 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 5 years ago
• DaveBerkeley / serv_soc
  SoC based on SERV, Olof Kindgren's bit-serial RISC-V processor. Provides Execute in Place (XiP) from Flash.
  ☆31Updated 4 years ago
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated this week