Alternatives and similar repositories for ZEF:

Users that are interested in ZEF are comparing it to the libraries listed below

• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆23Updated 4 years ago
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆21Updated 3 years ago
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆25Updated 5 years ago
• devsim / symdiff
  Symbolic differentation of algebraic expressions with Python and Tcl interfaces.
  ☆14Updated 2 months ago
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆18Updated this week
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 5 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆32Updated 2 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 4 years ago
• efabless / raptor
  Arm Cortex-M0 based Customizable SoC for IoT Applications
  ☆12Updated 4 years ago
• Qucs / qucs-help
  Qucs-Help documentation
  ☆11Updated 6 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆37Updated 4 months ago
• parallella / openeda
  Open source EDA chip design flow
  ☆49Updated 7 years ago
• mballance / fwrisc-s
  ☆10Updated 5 years ago
• efabless / ravenna
  32-bit RISC-V microcontroller
  ☆9Updated 3 years ago
• wsong83 / Asynchronous-Verilog-Synthesiser
  Synthesiser for Asynchronous Verilog Language
  ☆19Updated 10 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• lesc-ufv / cgra-routing
  SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
  ☆11Updated 4 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last year
• Xyce / Xyce_Regression
  The test suite for the Xyce Parallel Electronic Simulator
  ☆4Updated last week
• scale-lab / PVTsensors
  Designs for Process-Voltage-Temperature (PVT) Sensors with MCU
  ☆22Updated 4 years ago
• StanfordAHA / lake
  Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…
  ☆20Updated this week
• westonb / open-pmic
  A current mode buck converter on the SKY130 PDK
  ☆26Updated 3 years ago
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆39Updated 9 years ago
• The-OpenROAD-Project / OpeNPDN
  Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.
  ☆33Updated last year
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 4 years ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 6 years ago
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆25Updated 4 years ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆16Updated 5 years ago
• JinwooWang / Deep-Learning-For-Analog-Circuit-Sizing
  Combination of Analog Circuit Sizing and DL.
  ☆18Updated last year