Alternatives and similar repositories for ZEF

Users that are interested in ZEF are comparing it to the libraries listed below

• BerkeleyHCI / edg-ide
  ☆14Updated 2 months ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• s-holst / kyupy
  A Python package for high-performance processing and analysis of non-hierarchical VLSI designs
  ☆12Updated last year
• opencomputeproject / ODSA-CDXML
  TBD
  ☆12Updated 4 months ago
• libresilicon / coriolis
  autorouter forked from https://www-soc.lip6.fr/git/coriolis.git
  ☆15Updated 7 years ago
• f4pga / icestorm
  Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
  ☆34Updated 3 years ago
• TinyTapeout / tt-support-tools
  tools used by project repos to test configuration, generate OpenLane run summaries and documentation
  ☆22Updated last week
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• akukulanski / ADC_Sigma_Delta_VHDL
  Sigma-Delta Analog to Digital Converter in FPGA (VHDL)
  ☆16Updated 7 years ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated last month
• The-OpenROAD-Project / OpeNPDN
  Public repository for Task 6 of OpenROAD project. ML-based PDN synthesis and optimization.
  ☆33Updated last year
• gsomlo / yoloRISC
  A RocketChip rv64imac blinky for yosys/nextpnr/trellis & the Lattice ECP5 fpga
  ☆26Updated 5 years ago
• libresilicon / magic-8.2
  Magic VLSI Layout Tool
  ☆21Updated 5 years ago
• The-OpenROAD-Project / TritonSizer
  UCSD Sizer for leakage/dynamic power recovery, timing recovery
  ☆18Updated 6 years ago
• nkkav / yosys-examples
  Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)
  ☆22Updated 4 years ago
• Xyce / Xyce_Regression
  The test suite for the Xyce Parallel Electronic Simulator
  ☆4Updated 3 weeks ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 4 years ago
• YosysHQ / sby-gui
  GUI for SymbiYosys
  ☆15Updated last year
• Qucs / qucs-help
  Qucs-Help documentation
  ☆11Updated 6 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆50Updated 8 years ago
• warclab / dyract
  DyRACT Open Source Repository
  ☆16Updated 9 years ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆16Updated 6 years ago
• gh-code / libCircuit
  libCircuit is a C++ Library for EDA software development
  ☆18Updated 6 years ago
• efabless / ravenna
  32-bit RISC-V microcontroller
  ☆9Updated 3 years ago
• CedarEDA / CedarSim.jl
  Analog Circuit Simulator
  ☆21Updated 9 months ago
• masc-ucsc / anubis
  The ANUBIS benchmark suite for Incremental Synthesis
  ☆12Updated 4 years ago
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• m-labs / nmigen-soc
  System on Chip toolkit for nMigen
  ☆19Updated 5 years ago
• SymbiFlow / vtr-verilog-to-routing
  SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research
  ☆38Updated 10 months ago
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆13Updated 8 years ago