Alternatives and similar repositories for RS5

Users that are interested in RS5 are comparing it to the libraries listed below

• yathAg / openroad_vsd_7nmContest
  ☆16Updated 2 years ago
• snishizawa / libretto
  Characterizer
  ☆31Updated 2 months ago
• pulp-platform / artistic
  An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
  ☆22Updated last month
• mosbiuschip / chipathon2025
  Documentation for the 2025 IEEE SSCS Chipathon Track on MOSbius
  ☆13Updated 5 months ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆74Updated 3 years ago
• OS-EDA / Course
  Home of the open-source EDA course.
  ☆52Updated 8 months ago
• StefanSchippers / xschem_sky130
  XSCHEM symbol libraries for the Google-Skywater 130nm process design kit.
  ☆69Updated 2 months ago
• Intuity / forastero
  Making cocotb testbenches that bit easier
  ☆36Updated 3 months ago
• vlsiexcellence / Static-Timing-Analysis-Full-Course
  Static Timing Analysis Full Course
  ☆63Updated 3 years ago
• vsdip / vsdsram_sky130
  ☆41Updated 3 years ago
• laurentc2 / SKY130_for_KLayout
  KLayout technology files for Skywater SKY130
  ☆44Updated 2 years ago
• prasadp4009 / tbengy
  Python Tool for UVM Testbench Generation
  ☆55Updated last year
• praharshapm / vsdmixedsignalflow
  This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…
  ☆48Updated 5 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆99Updated 7 months ago
• iic-jku / osic-multitool
  JKU IIC OSIC-Multitool for open-source IC (OSIC) design for SKY130.
  ☆77Updated 10 months ago
• chipfoundry / nix-eda
  Nix derivations for EDA tools
  ☆11Updated 2 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆74Updated 2 months ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆82Updated 4 years ago
• AsFigo / yoYoLint
  SystemVerilog RTL Linter for YoSys
  ☆23Updated last year
• verilator / verilator-announce
  Announcements related to Verilator
  ☆44Updated 3 months ago
• stineje / CharLib
  Open-source repository for a standard-cell library characterizer using complete open-source tools
  ☆46Updated 3 weeks ago
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆43Updated 5 months ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆134Updated 2 years ago
• hanysalah / Design-Pattern-in-SV
  This repo is created to include illustrative examples on object oriented design pattern in SV
  ☆60Updated 2 years ago
• dineshannayya / riscduino_dcore
  ☆15Updated last year
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• MahmouodMagdi / Clock-Domain-Crossing-Synchronizers
  Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…
  ☆67Updated last year
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆79Updated 5 years ago
• Shehab-Naga / ddr5_phy
  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
  ☆74Updated last year
• merledu / caravan
  A caravan equipped with API for creating bus protocols in Chisel with ease.
  ☆14Updated 3 weeks ago