mortie / rv32i-logisim-cpuLinks
Implementation of RV32I in Logisim-evolution.
☆25Updated 2 years ago
Alternatives and similar repositories for rv32i-logisim-cpu
Users that are interested in rv32i-logisim-cpu are comparing it to the libraries listed below
Sorting:
- Quite OK image compression Verilog implementation☆23Updated last year
- A small and simple rv32i core written in Verilog☆17Updated 3 years ago
- KISCV, a KISS principle riscv32i CPU☆27Updated last year
- RV32I single cycle simulation on open-source software Logisim.☆21Updated 3 years ago
- ☆20Updated 8 months ago
- A simple risc-v CPU /GPU running on an Arty A7-100T FPGA board☆32Updated 4 years ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆65Updated 7 months ago
- ZPU Evo(lution), an enhanced ZPU microprocessor design in VHDL to embed within an FPGA including SoC functionality. Project currently use…☆15Updated 3 years ago
- Port TCC (Tiny C Compiler) to support Risc-V 32 targets (specifically for the ESP32-C3). This project is a work-in-progress and is not cu…☆73Updated 2 weeks ago
- Soft USB for LiteX☆50Updated 3 months ago
- Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).☆57Updated 2 years ago
- A Risc-V SoC for Tiny Tapeout☆45Updated last month
- Doom classic port to lightweight RISC‑V☆106Updated 3 years ago
- Minimal microprocessor☆21Updated 8 years ago
- FPGA Guide☆14Updated 4 years ago
- PCB combining Raspberry Pi Pico and iCE40 FPGA☆31Updated last year
- Design digital circuits in C. Simulate really fast with a regular compiler.☆177Updated this week
- Implementation of a RISC-V CPU in Verilog.☆17Updated 10 months ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆75Updated last week
- ☆15Updated 8 months ago
- Reusable Verilog 2005 components for FPGA designs☆49Updated last month
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆33Updated last year
- 5-stage RISC-V CPU, originally developed for RISCBoy☆35Updated 2 years ago
- Example Verilog code for Ulx3s☆41Updated 3 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆111Updated last month
- IEEE 754 single precision floating point library in systemverilog and vhdl☆39Updated 2 weeks ago
- Example of how to get started with olofk/fusesoc.☆19Updated 4 years ago
- ☆16Updated last year
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆71Updated 3 years ago
- Patched sources/configs for RISC-V Linux with musl-based toolchain targeting 8 MB RAM☆24Updated 3 years ago