jeanthom / gramLinks
DDR3 controller for nMigen (WIP)
☆14Updated last year
Alternatives and similar repositories for gram
Users that are interested in gram are comparing it to the libraries listed below
Sorting:
- There are many RISC V projects on iCE40. This one is mine.☆15Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆43Updated 4 months ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Use ECP5 JTAG port to interact with user design☆29Updated 3 years ago
- PicoRV☆44Updated 5 years ago
- iCE40 floorplan viewer☆24Updated 7 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- Smol 2-stage RISC-V processor in nMigen☆26Updated 4 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Updated 5 years ago
- Small footprint and configurable HyperBus core☆12Updated 2 years ago
- Cross compile FPGA tools☆21Updated 4 years ago
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆21Updated last year
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- RISC-V Processor written in Amaranth HDL☆38Updated 3 years ago
- PLEASE MOVE TO PAWSv2☆17Updated 3 years ago
- USB virtual model in C++ for Verilog☆31Updated 8 months ago
- USB 1.1 Device IP Core☆21Updated 7 years ago
- Simplified environment for litex☆14Updated 4 years ago
- Yosys Plugins☆21Updated 5 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Mini CPU design with JTAG UART support☆20Updated 4 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- Experiments with Yosys cxxrtl backend☆49Updated 5 months ago
- Minimal RISC-V RV32I CPU design as described in a companion blog post.☆12Updated 5 years ago
- Small footprint and configurable Inter-Chip communication cores☆59Updated 3 weeks ago
- ☆44Updated 3 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆22Updated this week
- Programmable multichannel ADPCM decoder for FPGA☆23Updated 4 years ago
- A padring generator for ASICs☆25Updated 2 years ago