Alternatives and similar repositories for gram

Users that are interested in gram are comparing it to the libraries listed below

• lambdaconcept / lambdaUSB
  A configurable USB 2.0 device core
  ☆31Updated 5 years ago
• lambdaconcept / lambdasoc
  ☆44Updated 6 months ago
• xobs / lxbuildenv
  Simplified environment for litex
  ☆14Updated 4 years ago
• whitequark / Yumewatari
  妖刀夢渡
  ☆60Updated 6 years ago
• kbeckmann / pergola_projects
  My pergola FPGA projects
  ☆30Updated 4 years ago
• tomverbeure / cxxrtl_eval
  Experiments with Yosys cxxrtl backend
  ☆49Updated 8 months ago
• YosysHQ / prjpeppercorn
  Project Peppercorn - GateMate FPGA Bitstream Documentation
  ☆25Updated last week
• xobs / valentyusb
  USB Full-Speed core written in migen/LiteX
  ☆12Updated 6 years ago
• litex-hub / litehyperbus
  Small footprint and configurable HyperBus core
  ☆13Updated 3 years ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 7 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆21Updated 4 years ago
• daveshah1 / ElasticC
  lightweight open HLS for FPGA rapid prototyping
  ☆20Updated 7 years ago
• mattvenn / logLUTs
  Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
  ☆21Updated last year
• knielsen / ice40_viewer
  ☆61Updated last year
• emeb / up5k_riscv
  There are many RISC V projects on iCE40. This one is mine.
  ☆15Updated 5 years ago
• gregdavill / litex-hyperram
  Standard HyperRAM core for ECP5 written in Litex/Migen
  ☆14Updated 5 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 6 years ago
• Wren6991 / Hazard2
  Smol 2-stage RISC-V processor in nMigen
  ☆26Updated 4 years ago
• tomverbeure / ecp5_jtag
  Use ECP5 JTAG port to interact with user design
  ☆32Updated 4 years ago
• YosysHQ / setup-oss-cad-suite
  Set up your GitHub Actions workflow with a OSS CAD Suite
  ☆16Updated last year
• m-labs / nmigen-boards
  Board and connector definition files for nMigen
  ☆30Updated 4 years ago
• kbob / nmigen-examples
  I want to learn [n]Migen.
  ☆42Updated 5 years ago
• ArcaneNibble / KinglerPAR
  Next-Generation FPGA Place-and-Route
  ☆10Updated 7 years ago
• daveshah1 / prjtrellis-dvi
  DVI video out example for prjtrellis
  ☆16Updated 6 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆45Updated 3 months ago
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆39Updated 3 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆46Updated 7 months ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 7 years ago
• icebreaker-fpga / icebreaker-amaranth-examples
  This repository contains iCEBreaker examples for Amaranth HDL.
  ☆39Updated last year
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago