warclab / idea
iDEA FPGA Soft Processor
☆16Updated 8 years ago
Alternatives and similar repositories for idea:
Users that are interested in idea are comparing it to the libraries listed below
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 8 months ago
- Open Processor Architecture☆26Updated 8 years ago
- Atom Hardware IDE☆13Updated 3 years ago
- The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…☆35Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated 2 weeks ago
- Fork of OpenCores jpegencode with Cocotb testbench☆43Updated 9 years ago
- Open source MPSoC running 620 MIPS (CHStone) of RISC-V (RV32iMC) programms on the ARTY board (XC7A35T).☆21Updated 5 years ago
- ☆20Updated 2 years ago
- ☆22Updated 8 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆74Updated 6 years ago
- JTAG DPI module for OpenRISC simulation with Verilator☆17Updated 12 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- Wishbone interconnect utilities☆39Updated last month
- Yosys Plugins☆21Updated 5 years ago
- Library of reusable VHDL components☆28Updated last year
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆27Updated 6 years ago
- RISC-V processor☆29Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 3 weeks ago
- a playground for xilinx zynq fpga experiments☆48Updated 6 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- This repository contains synthesizable examples which use the PoC-Library.☆36Updated 4 years ago
- simple hyperram controller☆11Updated 6 years ago
- Docker Development Environment for SpinalHDL☆19Updated 7 months ago
- A padring generator for ASICs☆25Updated last year
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- Torc: Tools for Open Reconfigurable Computing☆38Updated 7 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 7 years ago
- Triple Modular Redundancy☆25Updated 5 years ago
- A collection of debugging busses developed and presented at zipcpu.com☆40Updated last year