oprecomp / HLS_BLSTM
The community version of HLS_BLSTM (A BLSTM FPGA accelerator of an OCR appilcation, using CAPI/SNAP))
☆11Updated 5 years ago
Alternatives and similar repositories for HLS_BLSTM:
Users that are interested in HLS_BLSTM are comparing it to the libraries listed below
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆104Updated 6 years ago
- PYNQ, Neural network Language model, Overlay☆106Updated 5 years ago
- This project is trying to create a base vitis platform to run with DPU☆47Updated 4 years ago
- FPGA-based ZynqNet CNN accelerator developed by Vivado_HLS☆108Updated 7 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆56Updated 3 years ago
- Light-weighted neural network inference for object detection on small-scale FPGA board☆91Updated 5 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆28Updated 4 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆70Updated 5 years ago
- Convolutional Neural Network Using High Level Synthesis☆84Updated 4 years ago
- ☆88Updated 4 years ago
- Convolutional Neural Net written for implementation on an FPGA☆21Updated 7 years ago
- An HLS based winograd systolic CNN accelerator☆50Updated 3 years ago
- ☆121Updated 2 months ago
- This is the first step to implement RNN on FPGAs. All modules are heavily commented. We will use High-Level Synthesis to turn these code …☆22Updated 5 years ago
- At present, just an example to show how to map the detection algorithm YOLOv2 from model to FPGA☆31Updated 6 years ago
- FPGA and GPU acceleration of LeNet5☆35Updated 5 years ago
- Vitis HLS Library for FINN☆189Updated 3 weeks ago
- hls code zynq 7020 pynq z2 CNN☆79Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆46Updated 7 years ago
- This repository contains a "Hello World" introduction application to the Xilinx PYNQ framework.☆98Updated 2 years ago
- 基于HLS的高效深度卷积神经网络FPGA实现方法☆69Updated 5 years ago
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 6 years ago
- Training and Implementation of a CNN for image classification with binary weights and activations on FPGA with HLS tools☆48Updated 6 years ago
- ☆29Updated 7 years ago
- Zynq-7000 DPU TRD☆44Updated 5 years ago
- This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems u…☆38Updated 5 years ago
- Example of Tiny YOLO deployed using Xilinx BNN-PYNQ.☆31Updated 5 years ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 5 months ago
- FPGA-based neural network inference project for 2020 DAC System Design Contest☆111Updated 4 years ago
- Matrix Operation Library for FPGA https://xilinx.github.io/gemx/☆63Updated 5 years ago