An efficient implementation of the Viterbi decoding algorithm in Verilog
☆63Mar 15, 2024Updated 2 years ago
Alternatives and similar repositories for Viterbi-Decoder-in-Verilog
Users that are interested in Viterbi-Decoder-in-Verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Hardware Viterbi Decoder in verilog☆32May 28, 2019Updated 7 years ago
- This is about the implementation of (2,1,4) Convolutional Encoder and Viterbi Decoder using Verilog VHDL.☆14Aug 12, 2020Updated 5 years ago
- Turbo coder and decoder☆12Oct 11, 2023Updated 2 years ago
- Reference implementation of GFDM framework☆16Jun 14, 2018Updated 8 years ago
- Generalized Frequency Division Multiplexing (GFDM) library for MATLAB.☆17Jun 27, 2018Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- World's first Nintendo 3DS emulator for Apple devices based on Citra.☆18Apr 7, 2023Updated 3 years ago
- DVB-S2 LDPC Decoder☆30Jul 17, 2014Updated 11 years ago
- SPI to I2C Protocol Conversion Using Verilog. Final Year BTech project. Also published an IEEE paper.☆14Jul 28, 2021Updated 4 years ago
- Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS☆30Dec 17, 2020Updated 5 years ago
- MATLAB implementation of the DVB-S2 as in ETSI EN 302 307-1☆15Aug 26, 2021Updated 4 years ago
- A QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA☆238Nov 29, 2023Updated 2 years ago
- Открытое RISC-V процессорное ядро MIRISCV для образовательных целей☆30Dec 5, 2024Updated last year
- FuseSoc Verification Automation☆22Jul 21, 2022Updated 3 years ago
- The FPGA design for the FreeSRP's Artix 7 FPGA☆26Apr 12, 2017Updated 9 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Lime Digital Signal Processing☆29Nov 25, 2025Updated 7 months ago
- Verilog Code for an 8-bit ALU☆15Oct 29, 2016Updated 9 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆55Sep 17, 2017Updated 8 years ago
- Verilog VPI module to dump FST (Fast Signal Trace) databases☆20Sep 19, 2023Updated 2 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆43Dec 1, 2019Updated 6 years ago
- RTL Verilog library for various DSP modules☆99Feb 17, 2022Updated 4 years ago
- ☆10Nov 2, 2023Updated 2 years ago
- Matlab implementation of polar codes for a BEC☆11Dec 1, 2017Updated 8 years ago
- CNN-Aided Bit-Flipping for Belief Propagation Polar Decoder☆11Mar 12, 2021Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Reed-Solomon encode/decode error correction library, in ANSI C☆50Oct 24, 2021Updated 4 years ago
- This project contains synthesized verilog codes for Encryption/Decryption of secure IP stream using Advanced Encryption Standard (AES) al…☆17May 2, 2013Updated 13 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆92Updated this week
- An HBM FPGA based SpMV Accelerator☆19Aug 29, 2024Updated last year
- The USRP™ Hardware Driver FPGA Repository☆304Dec 13, 2021Updated 4 years ago
- Video Stream Scaler☆42Jul 17, 2014Updated 11 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 8 years ago
- ☆14Dec 15, 2017Updated 8 years ago
- Tiny Tapeout GDS Action (using LibreLane)☆23Jun 14, 2026Updated 2 weeks ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆27Jun 12, 2022Updated 4 years ago
- Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.☆475Jan 29, 2023Updated 3 years ago
- Repository containing the DSP gateware cores☆14Mar 9, 2026Updated 3 months ago
- A mixed-signal system on chip for nanopore-based DNA sequencing☆36Nov 30, 2022Updated 3 years ago
- Generic AXI to APB bridge☆13Jul 17, 2014Updated 11 years ago
- Minimal DVI / HDMI Framebuffer☆86Aug 9, 2020Updated 5 years ago
- Example applications for UHD/RFNoC☆20Mar 8, 2022Updated 4 years ago