jfoshea / Viterbi-Decoder-in-Verilog
An efficient implementation of the Viterbi decoding algorithm in Verilog
☆52Updated last year
Alternatives and similar repositories for Viterbi-Decoder-in-Verilog:
Users that are interested in Viterbi-Decoder-in-Verilog are comparing it to the libraries listed below
- Hardware Viterbi Decoder in verilog☆25Updated 5 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆35Updated 3 years ago
- Reed Solomon Encoder and Decoder Digital IP☆19Updated 4 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆63Updated last year
- RTL Verilog library for various DSP modules☆86Updated 3 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆49Updated 3 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆97Updated 9 months ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆55Updated 2 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆22Updated 5 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- Verilog based BCH encoder/decoder☆119Updated 2 years ago
- - Designed the LDPC decoder in the Matlab using the min-sum approach. - Designed quantized RTL in Verilog with the min-sum approach and …☆49Updated 7 years ago
- A collection of phase locked loop (PLL) related projects☆104Updated last year
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆47Updated 5 years ago
- Must-have verilog systemverilog modules☆33Updated 2 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- DVB-S2 LDPC Decoder☆27Updated 10 years ago
- IEEE 802.11 OFDM-based transceiver system☆33Updated 7 years ago
- PCIE 5.0 Graduation project (Verification Team)☆68Updated last year
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.☆152Updated 3 years ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆63Updated last month
- NMS_decode☆13Updated 4 years ago
- Reed Solomon Decoder (204,188)☆12Updated 10 years ago
- 最小和算法实现☆10Updated 4 years ago
- ☆30Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- FFT implement by verilog_测试验证已通过☆54Updated 8 years ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit MSK☆56Updated 5 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆30Updated 6 months ago