Alternatives and similar repositories for ascon:

Users that are interested in ascon are comparing it to the libraries listed below

• A-suozhang / Verilog_Uart_With_Fifo
  Implemented The UART with FIFO
  ☆13Updated 5 years ago
• aneeshkandi14 / ascon-hw-public
  ☆21Updated 9 months ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆17Updated 5 years ago
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 5 years ago
• ljgibbslf / SM2_core
  opensource crypto IP core
  ☆27Updated 4 years ago
• ljhsiun2 / EllipticCurves_SystemVerilog
  Elgamal's over Elliptic Curves
  ☆19Updated 6 years ago
• ecelab-org / Split-Chip_authentication
  An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.
  ☆15Updated 5 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆21Updated 7 years ago
• hyperpicc / ecc
  Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)
  ☆19Updated 7 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆89Updated 5 years ago
• ascon / ascon-hardware
  NIST LWC Hardware Reference Implementation of Ascon v1.2
  ☆25Updated last year
• BalaDhinesh / Accelerating_Standard_and_Modified_AES128
  Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms
  ☆25Updated 3 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 7 years ago
• adnanbaysal / TRNG-with-Ring-Oscillators-in-Verilog
  A true random number generator with ring oscillators structure written in VHDL targeting FPGA's.
  ☆10Updated 4 years ago
• lajanugen / Modular-Exponentiation
  Verilog Implementation of modular exponentiation using Montgomery multiplication
  ☆32Updated 10 years ago
• raymondrc / FPGA_SM4
  FPGA implementation of Chinese SM4 encryption algorithm.
  ☆50Updated 7 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆64Updated 5 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆51Updated 4 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆40Updated last year
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆50Updated last year
• fatestudio / RSA4096_NEW
  ☆13Updated 9 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆60Updated 7 months ago
• ovpanait / zynq-aes
  AES hardware engine for Xilinx Zynq platform
  ☆30Updated 3 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• AnuragSChatterjee / Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA
  A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…
  ☆14Updated last year
• spike556 / HuffmanCode
  hardware implement of huffman coding(written in verilog)
  ☆11Updated 7 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆151Updated 3 years ago